SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 146

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Bus Interface Unit
6.2.4
6.2.5
6-6
Byte and halfword accesses
AHB system considerations
This section describes byte and halfword accesses for:
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•
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Address alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB
addresses to the necessary boundary. 16-bit accesses are aligned to halfword
boundaries, and 32-bit accesses to word boundaries.
Thumb instruction fetches
All instruction fetches, irrespective of the state of the ARM9EJ-S core, are made as
32-bit accesses on the AHB. If the ARM9EJ-S core is in Thumb state, then two
instructions can be fetched at a time.
Endianness and byte lane indication
The AMBA Specification (Rev 2.0) does not specify any explicit support for endianness.
The ARM926EJ-S processor provides a supplementary signal, DHBL, that indicates
which bytes are to be updated for write transfers and which bytes should contain valid
data for reads. This is created using the address, and the endianness of the access.
The CFGBIGEND signal indicates the current endianness setting used by the
ARM9EJ-S core, and reflects the value held in CP15 c1 (see Control Register c1 on
page 2-12).
Because writes are buffered, the value of the CFGBIGEND signal might be
inconsistent with DHBL if the write-buffer is not drained before changing the
endianness setting in the control register.
DHBL is encoded in little-endian format. For example, a value of b0001 indicates byte
0 in little-endian mode, and byte 3 in big-endian mode.
This section describes AHB considerations for:
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•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
Address alignment
Thumb instruction fetches
Endianness and byte lane indication.
Single-layer AHB systems on page 6-7
Multi-layer AHB systems on page 6-7
Multi-AHB systems on page 6-8
ARM DDI0198D