SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 173

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
9.2
9.2.1
9.2.2
9.2.3
ARM DDI0198D
IMB operation
Drain the write buffer
Clean the DCache
Synchronize data and instruction streams in level two AHB subsystems
To ensure consistency between data and instruction sides, you must take the following
steps:
1.
2.
3.
4.
5.
If the cache contains cache lines corresponding to write-back regions of memory, then
it might contain dirty entries. These entries must be cleaned to make external memory
consistent with the DCache. If only a small part of the cache has to be cleaned, then this
can be done by using a sequence of clean DCache single entry instructions, or if the
entire cache has to be cleaned, then this can be done efficiently using the test and clean
instruction. See Cache Operations Register c7 on page 2-20 for details of cache
maintenance operations.
Executing a drain write buffer instruction causes the ARM9EJ-S core to wait until
outstanding buffered writes have completed on the AHB interface. This includes writes
that occur as a result of data being written back to main memory because of clean
operations, and data for store instructions.
The level two AHB subsystem might also require explicit synchronization between data
and instruction sides. It is possible for the data and instruction AHB masters to be
attached to different AHB subsystems. Even if both masters are present on the same bus,
some form of separate ICache might exist for performance reasons, and this has to be
invalidated to ensure consistency.
The process of synchronizing instructions and data in level two memory must be
invoked using some form of fully blocking operation. This is to ensure that the end of
the operation can be determined using software. It is recommended that either a
nonbuffered store (
synchronization.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Clean the DCache
Drain the write buffer
Synchronize data and instruction streams in level two AHB subsystems
Invalidate the ICache on page 9-4
Flush the prefetch buffer on page 9-4.
) or a noncached load (
) is used to trigger external
Instruction Memory Barrier
9-3

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