SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 197

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

A.5
ARM DDI0198D
JTAG signals
Table A-4 describes the ARM926EJ-S processor JTAG signals.
Name
DBGIR[3:0]
TAP controller
instruction register
DBGnTRST
Not test reset
DBGnTDOEN
Not DBGTDO enable
DBGSCREG[4:0]
DBGSDIN
External scan chain
serial input data
DBGSDOUT
External scan chain
serial data output
DBGTAPSM[3:0]
TAP controller state
machine
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Output
Input
Output
Output
Output
Input
Output
Input
Input
Output
Input
Description
These four bits reflect the current instruction loaded
into the TAP controller instruction register. These bits
change when the TAP controller is in the
UPDATE-IR state.
This is the active LOW reset signal for the
EmbeddedICE-RT internal state. This signal is a
level-sensitive asynchronous reset input.
When LOW, indicates that the serial data is being
driven out of the DBGTDO output. Normally used as
an output enable for a DBGTDO pin in a packaged
part.
These five bits reflect the ID number of the scan chain
currently selected by the TAP controller. These bits
change when the TAP controller is in the
UPDATE-DR state.
Contains the serial data to be applied to an external
scan chain.
Contains the serial data out of an external scan chain.
When an external scan chain is not connected, this
signal must be tied LOW.
This bus reflects the current state of the TAP
controller state machine.
Synchronous test clock enable.
Test data input for debug logic.
Test data output from debug logic.
Test mode select for TAP controller.
Table A-4 JTAG signals
Signal Descriptions
A-9