SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 198

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Descriptions
A.6
A-10
Miscellaneous signals
Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor.
Name
BIGENDINIT
CLK
CFGBIGEND
ARM9EJ-S core
endianness
configuration
EXTEST
INTEST
nFIQ
Not fast interrupt
request
nIRQ
Not interrupt
request
SCANENABLE
STANDBYWFI
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Input
Input
Output
Input
Input
Input
Input
Input
Output
Description
Determines the setting of the B bit in CP15 c1 after a
system reset. When HIGH the reset state of the B bit is 1
(big-endian). When LOW the reset state of the B bit is 0
(little-endian).
This clock times all operations of the ARM926EJ-S
design. All outputs change from the rising edge and all
inputs are sampled on the rising edge. The clock can be
stretched in either phase. Through the use of the
DHCLKEN and IHCLKEN signals, this clock also times
AHB operations. Through the use of the DBGTCKEN
signal, this clock also controls JTAG and debug operations.
This signal reflects the setting of the B bit in CP15 c1.
When HIGH, the processor treats bytes in memory as
being in big-endian format. When LOW, memory is treated
as little-endian.
EXTEST mode test signal. This signal must be LOW
during normal operation.
during normal operation.
This is the fast interrupt request signal. This signal must be
synchronous to CLK.
This is the interrupt request signal. This signal must be
synchronous to CLK.
normal operation.
When HIGH indicates that the ARM926EJ-S processor is
in wait for interrupt mode.
INTEST mode test signal. This signal must be LOW
Scan enable test signal. This signal must be LOW during
Table A-5 Miscellaneous signals
ARM DDI0198D