SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 200

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Descriptions
A.7
A-12
ETM interface signals
Table A-6 describes the ARM926EJ-S processor ETM interface signals.
Name
ETMBIGEND
ETMCHSD[1:0]
ETMCHSE[1:0]
ETMDA[31:0]
ETMDABORT
ETMDBGACK
ETMDMAS[1:0]
ETMDMORE
ETMDnMREQ
ETMDnRW
ETMDSEQ
ETMEN
ETMHIVECS
ETMIA[31:0]
ETMIABORT
ETMID15TO11[15:11]
ETMID31TO25[31:25]
ETMIJBIT
ETMInMREQ
ETMINSTREXEC
ETMINSTRVALID
ETMISEQ
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
ETM big-endian configuration indication.
ETM coprocessor handshake decode signals.
ETM coprocessor handshake execute signals.
ETM data address.
ETM data abort.
ETM debug mode indication.
ETM data size indication.
ETM more sequential data indication.
ETM data memory request.
ETM data not read/write.
ETM sequential data indication.
Synchronous ETM interface enable. This signal
must be tied LOW if an ETM is not used.
ETM exception vectors configuration.
ETM instruction address.
ETM instruction abort.
ETM instruction data field bits [15:11].
ETM instruction data field bits [31:25].
ETM Jazelle state indication.
ETM instruction memory request.
ETM instruction execute indication.
ETM instruction valid indication.
ETM sequential instruction access.
Table A-6 ETM interface signals
ARM DDI0198D