SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 208

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

CP15 Test and Debug Registers
B.1
B.1.1
B-2
About the Test and Debug Registers
Debug Override Register
31
Cond
The ARM926EJ-S Test and Debug Registers, CP15 c15, provide additional
device-specific test operations. You can use the registers to access and control the
following:
•
•
•
•
•
•
•
You must only use these operations for test. The ARM Architecture Reference Manual
describes this register as implementation-defined.
The format of the CP15 test and debug operations is:
The MRC and MCR bit pattern is shown in Figure B-1.
The L bit distinguishes between an MCR (L = 1) and an MRC (L = 0).
You can use the Debug Override Register to modify the behavior of the ARM926EJ-S
core from the default behavior.
The function of each ARM926EJ-S Debug Override Register bit is shown in Table B-1
on page B-3.
The Debug Override Register can be accessed by using the following instructions:
28 27 26 25 24 23
Copyright © 2001-2003 ARM Limited. All rights reserved.
1 1 1 0
Debug Override Register
Debug and Test Address Register on page B-4
Trace Control Register on page B-5
MMU test operations on page B-5
Cache Debug Control Register on page B-12
MMU Debug Control Register on page B-13
Memory Region Remap Register on page B-15.
Opcode
_1
21 20 19
L
CRn
16 15
Figure B-1 CP15 MRC and MCR bit pattern
Rd
12 11 10 9 8 7
1 1 1 1
Opcode
_2
5 4 3
1
ARM DDI0198D
CRm
0