SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 210

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

CP15 Test and Debug Registers
B.1.2
B-4
Debug and Test Address Register
Bit 15, disable block-level clock gating
Bit 16, disable NC instruction prefetching
Bits 17 & 18, abort instruction TLB miss
Bit 19, test and clean all
This register defines the address used for debug and test operations, and for MMU test
operations using the MMU Test Register.
You can access the Debug and Test Address Register using the following instructions:
Copyright © 2001-2003 ARM Limited. All rights reserved.
You can use this bit to disable block-level clock gating with the
ARM926EJ-S processor. This bit does not affect the functionality of the
ARM926EJ-S processor. It allows the benefits of block-level clock gating
to be evaluated without the requirement to build two different
implementations of the ARM926EJ-S macrocell, one with block-level
clock gating, one without.
You can use this bit to disable speculative prefetching for instructions in
noncachable areas of memory. The default behavior of ARM926EJ-S
processor is to perform speculative sequential instruction fetches on the
AHB interface. Disabling prefetching prevents any speculative
noncachable instruction prefetches by the ARM926EJ-S memory
system, and only instruction requests issued by the ARM9EJ-S core
result in instruction fetches on the AHB interface.
You can use the abort data TLB miss and abort instruction TLB miss bits
to prevent page table walks occurring as the result of a TLB miss. When
set, a TLB miss results in the access being aborted as if the access has
resulted in a translation fault, and a value of
status field of the appropriate FSR.
You can use the test-and-clean-all bit to modify the behavior of the test
and clean, and test clean and invalidate instructions so that a single
instruction can be used to clean or clean and invalidate the entire cache.
This is only intended for use by a debugger, to provide an efficient way
to clean the data cache using scan chain 15.
being written into the
ARM DDI0198D