SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 212

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

CP15 Test and Debug Registers
B-6
31
Instruction
30
Inserting or reading entries in the main TLB
Use this procedure to access entries in the main TLB:
1.
Way
Bit
[31]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Use the following Debug and Test Address Register instruction to access a main
TLB entry:
The Rd register selects the main TLB entry as Figure B-2 shows.
Table B-4 describes the Rd register entry-select bit fields.
Name
Way
SBZ
Table B-4 Encoding of the main TLB entry-select bit fields
Table B-3 MMU test operation instructions (continued)
Operation
Read PA and access permission data in main TLB entry
Write PA and access permission data data in main TLB entry
Transfer main TLB entry into RAM
Read tag in lockdown TLB entry
Write tag in lockdown TLB entry
Read PA and access permission data in lockdown TLB entry
Write PA and access permission data in lockdown TLB entry
Transfer lockdown TLB entry into RAM
Definition
Way select:
1 = way 1
0 = way 0.
Figure B-2 Rd format for selecting main TLB entry
15
14
Indexed entry
10
9
SBZ
ARM DDI0198D
0