SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 216

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

CP15 Test and Debug Registers
B-10
On the rising clock edge when MMUxCS=1, the data on MMUxWD is written into the
data RAM. The exact index is on MMUxADDR (as specified in the Test and Debug
Address Register). The lanes written are controlled by the MMUxWE[3:0] pins. The
mapping is as follows:
MMUxWE[0]: 0= read, 1= write MMUxWD[ 29: 0] into RAM
MMUxWE[1]: 0= read, 1= write MMUxWD[ 55:30] into RAM
MMUxWE[2]: 0= read, 1= write MMUxWD[ 85:57] into RAM
MMUxWE[3]: 0= read, 1= write MMUxWD[111:86] into RAM
In the case of the main MMU, the output enable MMUxOE is driven at all times. The
MMUxRD data bus must be strongly driven at all times. The controller samples the data
from the MMUxRD data bus when a read is being performed.
Inserting or reading entries in the lockdown TLB
Use this procedure to access entries in the lockdown TLB:
1.
MMUxADDR
MMUxWD
MMUxWE
Copyright © 2001-2003 ARM Limited. All rights reserved.
MMUxOE
MMUxCS
MMUxRD
Use the following Debug and Test Address Register instruction to access a
lockdown TLB entry:
The Rd register selects the lockdown TLB entry as shown in Figure B-6 on
page B-11.
Note
CLK
WDATA
LOC
IDX
RDATA
Figure B-5 Write to the data RAM
ARM DDI0198D