SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 219

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.1.6
ARM DDI0198D
MMU Debug Control Register
Forcing write-through behavior
Setting the DWB bit to 1 forces the DCache to treat all cachable accesses as though they
were in a write-through region of memory. The setting of the DWB bit overrides any
setting specified in either the MMU page tables or in the Memory Region Remap
Register.
If the cache contains dirty cache lines, these remain dirty while the DWB bit is set,
unless they are written back because of a write-back eviction after a linefill, or because
of an explicit clean operation.
Lines that are clean are not marked as dirty if they are updated while the DWB bit is set.
This functionality allows a debugger to download code or data to external memory,
without the requirement to clean part or all of the DCache to ensure that the code or data
being downloaded has been written to external memory.
If the DWB bit is set, and a write is made to a cache line that is dirty, then both the cache
line and external memory are updated with the write data. Other entries in the cache line
still have to be written back to main memory to achieve coherency.
Disabling cache linefills
Setting the DDL and DIL bits prevents the relevant cache from updating when
performing a linefill on a miss. When set, a linefill is performed on a cache miss, reading
eight words from external memory, but the cache is not updated with the linefill data.
The memory region mapping is unchanged. This mode of operation is required for
debug so that the memory image, as seen by the ARM9EJ-S core, can be examined in a
non-invasive manner. Cache hits from a cachable region read data words from the cache,
and cache misses from a cachable region read words directly from memory.
You can use the MMU Debug Control Register to enable TLB and micro TLB entries
to be preserved during debug. For debug to be non-invasive, bits [5:0] must be set to
b111111 prior to changing any other CP15 registers, or issuing any system speed load
or store. If main TLB loading is disabled, page table walks still take place, but the
resultant data is forwarded around the TLB.
It might be necessary to temporarily change the contents of a page table entry to
facilitate debug operations. Disabling main TLB matches using bit 6 or 7 enables the
modified contents of the page table to be used for an access without having to invalidate
any entries in the main TLB.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
CP15 Test and Debug Registers
B-13