SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 221

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.1.7
ARM DDI0198D
Memory Region Remap Register
31
Bit
[3]
[2]
[1]
[0]
The read/write Memory Region Remap Register overrides the setting specified in the
MMU page tables, and the default behavior if the MMU is disabled.
The Memory Region Register has four fields for remapping instruction-side memory
regions and four fields for remapping data-side memory regions.
You can access the Memory Region Remap Register with the instructions in
Table B-11.
Figure B-9 shows the bit fields of the Memory Region Remap Register.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Name
DIUTM
DDUTM
DIUTL
DDUTL
Table B-10 MMU Debug Control Register bit assignments (continued)
SBZ
Function
Disable instruction micro TLB match
Disable data micro TLB match
Disable instruction micro TLB load
Disable data micro TLB load
Instruction
Table B-11 Memory Region Remap Register instructions
Figure B-9 Memory Region Remap Register format
16
15
IWB
14
13
IWT
12 11
Operation
Read Memory Region Remap Register
Write Memory Region Remap Register
INCNB
INCB
10
Description
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
0 = Enable D-micro TLB match
1 = Disable D-micro TLB match
0 = Enable D-micro TLB load
1 = Disable D-micro TLB load
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
CP15 Test and Debug Registers
9
8 7
DWB
DNCNB
6
DNCB
DWT
5
4 3
2
1
B-15
0