SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 227

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Architecture
ARM instruction
ARM state
ASIC
ASSP
ATPG
Automatic Test Pattern Generation (ATPG)
Back-annotation
Banked registers
Base register
Base register write-back
Beat
Big-endian
ARM DDI0198D
The organization of hardware and/or software that characterizes a processor and its
attached components, and enables devices with similar characteristics to be grouped
together when describing their behavior, for example, Harvard architecture, instruction
set architecture, ARMv6 architecture.
Is a word that specifies an operation for an ARM processor to perform. ARM
instructions must be word-aligned.
A processor that is executing ARM (32-bit) word-aligned instructions is operating in
ARM state.
See Application Specific Integrated Circuit.
See Application Specific Standard Part/Product.
See Automatic Test Pattern Generation.
The process of automatically generating manufacturing test vectors for an ASIC design,
using a specialized software tool.
The process of applying timing characteristics from the implementation process onto a
model.
Those physical registers whose use is defined by the current processor mode. The
banked registers are r8 to r14.
A register specified by a load or store instruction that is used to hold the base value for
the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the
virtual address which is sent to memory.
Updating the contents of the base register used in an instruction target address
calculation so that the modified address is changed to the next higher or lower
sequential address in memory. This means that it is not necessary to fetch the target
address for successive instruction transfers and enables faster burst accesses to
sequential memory.
Alternative word for an individual transfer within a burst. For example, an INCR4 burst
comprises four beats.
See also Burst.
Byte ordering scheme in which bytes of decreasing significance in a data word are
stored at increasing addresses in memory.
See also Little-endian and Endianness.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Glossary-3
Glossary