SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 232

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Glossary
Data Abort
Data cache
DBGTAP
DCache
Debugger
Debug Test Access Port (DBGTAP)
Direct-mapped cache
Direct Memory Access (DMA)
Dirty
DMA
DNM
Glossary-8
An indication from a memory system to a core that it must halt execution of an
attempted illegal memory access. A Data Abort is attempting to access invalid data
memory.
See also Abort, External Abort, and Prefetch Abort.
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used data. This is done to
greatly reduce the average speed of memory accesses and so to increase processor
performance.
See Debug Test Access Port.
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used data. This is done to
greatly reduce the average speed of memory accesses and so to increase processor
performance.
A debugging system that includes a program, used to detect, locate, and correct software
faults, together with custom hardware that supports software debugging.
The collection of four mandatory and one optional terminals that form the input/output
and control interface to a JTAG boundary-scan architecture. The mandatory terminals
are DBGTDI, DBGTDO, DBGTMS, and TCK. The optional terminal is TRST
(DBGnTRST). This signal is mandatory in ARM cores because it is used to reset the
debug logic.
A one-way set-associative cache. Each cache set consists of a single cache line, so cache
look-up selects and checks a single cache line.
An operation that accesses main memory directly, without the processor performing any
accesses to the data concerned.
A cache line in a write-back cache that has been modified while it is in the cache is said
to be dirty. A cache line is marked as dirty by setting the dirty bit. If a cache line is dirty,
it must be written to memory on a cache miss because the next level of memory contains
data that has not been updated. The process of writing dirty data to main memory is
called cache cleaning.
See also Clean.
See Direct Memory Access.
See Do Not Modify.
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