SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 233

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Domain
Do Not Modify (DNM)
Doubleword
Doubleword-aligned
EmbeddedICE logic
EmbeddedICE-RT
Embedded Trace Buffer
Embedded Trace Macrocell (ETM)
Endianness
ETM
Event
ARM DDI0198D
A collection of sections, large pages and small pages of memory, which can have their
access permissions switched rapidly by writing to the Domain Access Control Register
(CP15 register c3).
In Do Not Modify fields, the value must not be altered by software. DNM fields read as
Unpredictable values, and must only be written with the same value read from the same
field on the same processor.
Throughout this manual, DNM fields are sometimes followed by RAZ or RAO in
parentheses to show which way the bits should read for future compatibility, but
programmers must not rely on this behavior.
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise
stated.
A data item having a memory address that is divisible by 8.
An on-chip logic block that provides TAP-based debug support for ARM processor
cores. It is accessed through the TAP controller on the ARM core using the JTAG
interface.
The JTAG-based hardware provided by debuggable ARM processors to aid debugging
in real-time.
The ETB provides on-chip storage of trace data using a configurable sized RAM.
A hardware macrocell which, when connected to a processor core, outputs instruction
and data trace information on a trace port. The ETM provides processor driven trace
through a trace port compliant to the ATB protocol.
Byte ordering. The scheme that determines the order in which successive bytes of a data
word are stored in memory. An aspect of the system’s memory mapping.
See also Little-endian and Big-endian
See Embedded Trace Macrocell.
1 (Simple) An observable condition that can be used by an ETM to control aspects of a
trace.
2 (Complex) A boolean combination of simple events that is used by an ETM to control
aspects of a trace.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Glossary-9
Glossary