SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 238

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Glossary
Modified Virtual Address (MVA)
Monitor debug-mode
MPU
Multi-ICE
MVA
NCB
NCNB
Noncachable
Buffered
Noncachable
Nonbufferable
PA
Penalty
Power-on reset
Prefetching
Prefetch Abort
Glossary-14
A Virtual Address produced by the ARM processor can be changed by the current
Process ID to provide a Modified Virtual Address (MVA) for the MMUs and caches.
See also Fast Context Switch Extension.
One of two mutually exclusive debug modes. In Monitor debug-mode the processor
enables a software abort handler provided by the debug monitor or operating system
debug task. When a breakpoint or watchpoint is encountered, this enables vital system
interrupts to continue to be serviced while normal program execution is suspended.
See also Halt mode.
See Memory Protection Unit.
A JTAG-based tool for debugging embedded systems.
See Modified Virtual Address.
See Noncachable Buffered.
See Noncachable Nonbufferable.
Is a memory region where reads are performed from main memory and are not allocated
to the cache. Writes are performed to main memory through a write buffer, so processor
core execution can continue while the write is completed to main memory.
Is a memory region where reads are performed from main memory and are not allocated
to the cache. Writes are performed to main memory without buffering, so processor core
execution is halted while the write is completed.
See Physical Address.
The number of cycles in which no useful Execute stage pipeline activity can occur
because an instruction flow is different from that assumed or predicted.
See Cold reset.
In pipelined processors, the process of fetching instructions from memory to fill up the
pipeline before the preceding instructions have finished executing. Prefetching an
instruction does not mean that the instruction has to be executed.
An indication from a memory system to a core that it must halt execution of an
attempted illegal memory access. A Prefetch Abort can be caused by the external or
internal memory system as a result of attempting to access invalid instruction memory.
See also Data Abort, External Abort and Abort.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D

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