SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 24

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Introduction
1.1
1-2
About the ARM926EJ-S processor
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose
microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all
important.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction
sets, enabling the user to trade off between high performance and high code density. The
ARM926EJ-S processor includes features for efficient execution of Java byte codes,
providing Java performance similar to JIT, but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic
to assist in both hardware and software debug. The ARM926EJ-S processor has a
Harvard cached architecture and provides a complete high-performance processor
subsystem, including:
The ARM926EJ-S processor provides support for external coprocessors enabling
floating-point or other application-specific hardware acceleration to be added. The
ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM926EJ-S processor is a synthesizable macrocell. This means that you can
optimize the macrocell for a particular target library, and that you can configure the
memory system to suit your target application. You can individually configure the cache
sizes to be any power of two between 4KB and 128KB.
The tightly-coupled instruction and data memories are instantiated externally to the
ARM926EJ-S macrocell, providing you with the flexibility of optimizing the memory
subsystem for performance, power, and particular RAM type. The TCM interfaces
enable nonzero wait state memory to be attached, as well as providing a mechanism for
supporting DMA.
Figure 1-1 on page 1-3 shows the main blocks in the ARM926EJ-S processor.
Copyright © 2001-2003 ARM Limited. All rights reserved.
an ARM9EJ-S integer core
a Memory Management Unit (MMU)
separate instruction and data AMBA AHB bus interfaces
separate instruction and data TCM interfaces.
ARM DDI0198D

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