SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 32

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.2.1
2.2.2
2-4
Addresses in an ARM926EJ-S system
Accessing CP15 registers
Domain
Address type
All CP15 register bits that are defined and contain state are set to 0 by Reset except:
•
•
•
Three distinct types of address exist in an ARM926EJ-S system. Table 2-2 shows the
address types in ARM926EJ-S processor.
This is an example of the address manipulation that occurs when the ARM9EJ-S core
requests an instruction:
1.
2.
3.
4.
You can only access CP15 registers with MRC and MCR instructions in a privileged
mode. The instruction bit pattern of the MCR and MRC instructions is shown in
Figure 2-1 on page 2-5.
Copyright © 2001-2003 ARM Limited. All rights reserved.
The V bit is set to 0 at reset if the VINITHI signal is LOW, or 1 if the VINITHI
signal is HIGH.
The B bit is set to 0 at reset if the BIGENDINIT signal is LOW, or 1 if the
BIGENDINIT signal is HIGH.
The instruction TCM is enabled at reset if the INITRAM pin is HIGH. This
enables booting from the instruction TCM and sets the ITCM bit in the ITCM
region register to 1.
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated using the FCSE PID value to the MVA. The Instruction
Cache (ICache) and Memory Management Unit (MMU) detect the MVA (see
Process ID Register c13 on page 2-33).
If the protection check carried out by the MMU on the MVA does not abort and
the MVA tag is in the ICache, the instruction data is returned to the ARM9EJ-S
core.
If the protection check carried out by the MMU on the MVA does not abort, and
the cache misses (the MVA tag is not in the cache), then the MMU translates the
MVA to produce the PA. This address is given to the AMBA bus interface to
perform an external access.
ARM9EJ-S
Virtual Address (VA)
Caches and MMU
Modified Virtual Address (MVA)
Table 2-2 Address types in ARM926EJ-S
TCM and AMBA bus
Physical Address (PA)
ARM DDI0198D