SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 4

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
iv
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Caches and Write Buffer
4.1
4.2
4.3
4.4
4.5
Tightly-Coupled Memory Interface
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Bus Interface Unit
6.1
6.2
Noncachable Instruction Fetches
7.1
Coprocessor Interface
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Instruction Memory Barrier
9.1
9.2
9.3
Embedded Trace Macrocell Support
10.1
Copyright © 2001-2003 ARM Limited. All rights reserved.
About the caches and write buffer .............................................................. 4-2
Write buffer ................................................................................................. 4-4
Enabling the caches ................................................................................... 4-5
TCM and cache access priorities ............................................................... 4-8
Cache MVA and Set/Way formats .............................................................. 4-9
About the tightly-coupled memory interface ............................................... 5-2
TCM interface signals ................................................................................. 5-4
TCM interface bus cycle types and timing .................................................. 5-8
TCM programmer’s model ........................................................................ 5-19
TCM interface examples ........................................................................... 5-20
TCM access penalties .............................................................................. 5-29
TCM write buffer ....................................................................................... 5-30
Using synchronous SRAM as TCM memory ............................................ 5-31
TCM clock gating ...................................................................................... 5-32
About the bus interface unit ........................................................................ 6-2
Supported AHB transfers ............................................................................ 6-3
About noncachable instruction fetches ....................................................... 7-2
About the ARM926EJ-S external coprocessor interface ............................ 8-2
LDC/STC .................................................................................................... 8-4
MCR/MRC .................................................................................................. 8-6
CDP ............................................................................................................ 8-8
Privileged instructions ................................................................................. 8-9
Busy-waiting and interrupts ...................................................................... 8-10
CPBURST ................................................................................................ 8-11
CPABORT ................................................................................................ 8-12
nCPINSTRVALID ..................................................................................... 8-13
Connecting multiple external coprocessors .............................................. 8-14
About the instruction memory barrier operation ......................................... 9-2
IMB operation ............................................................................................. 9-3
Example IMB sequences ............................................................................ 9-5
About Embedded Trace Macrocell support .............................................. 10-2
ARM DDI0198D