SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 42

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2-14
Effects of Control Register on caches
The bits of the Control Register that directly affect the ICache and DCache behavior are:
•
•
•
Bit
[13]
[12]
[11:10]
[9]
[8]
[7]
[6:3]
[2]
[1]
[0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
the M bit
the C bit
the I bit
Name
V bit
I bit
-
R bit
S bit
B bit
-
C bit
A bit
M bit
Function
Location of exception vectors:
0 = Normal exception vectors selected, address range =
1 = High exception vectors selected, address range =
Set to the value of VINITHI on reset.
ICache enable/disable:
0 = ICache disabled
1 = ICache enabled.
SBZ.
ROM protection.
This bit modifies the ROM protection system. See Domain access
control on page 3-24.
System protection.
This bit modifies the MMU protection system. See Domain access
control on page 3-24.
Endianness: 0 = Little-endian operation 1 = Big-endian operation. Set to
the value of BIGENDINIT on reset.
Reserved. SBO.
DCache enable/disable:
0 = Cache disabled
1 = Cache enabled.
Alignment fault enable/disable:
0 = Data address alignment fault checking disabled
1 = Data address alignment fault checking enabled.
MMU enable/disable:
0 = disabled
1 = enabled.
Table 2-11 Control bit functions register c1 (continued)
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ARM DDI0198D
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