SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 44

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2-16
TCM
Instruction
TCM disabled
Instruction
TCM enabled
Instruction
TCM enabled
Instruction
TCM enabled
Data TCM
disabled
Data TCM
enabled
Data TCM
enabled
Data TCM
enabled
MMU
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
Enabled
Effects of the Control Register on TCM interface
The M bit of the Control Register, when combined with the En bit in the respective TCM
region register c9, directly affects the TCM interface behavior, as shown in Table 2-13.
Cache
ICache
disabled
ICache
disabled
ICache
enabled
ICache
enabled
DCache
disabled
DCache
disabled
DCache
enabled
DCache
enabled
Copyright © 2001-2003 ARM Limited. All rights reserved.
Behavior
All instruction fetches are from the external memory (AHB).
All instruction fetches are from the TCM interface, or from external memory
(AHB), depending on the setting of the base address in the instruction TCM
region register. No protection checks are made. All addresses are flat mapped.
That is, VA = MVA= PA.
All instruction fetches are from the TCM interface, or from the ICache,
depending on the setting of the base address in the Instruction TCM region
register. No protection checks are made. All addresses are flat mapped. That is,
VA = MVA= PA.
All instruction fetches are from the TCM interface, or from the ICache/AHB
interface, depending on the setting of the base address in the Instruction TCM
region register. Protection checks are made. All addresses are remapped from
VA to PA, depending on the page entry. That is, the VA is translated to an MVA,
and the MVA is remapped to a PA.
All data accesses are to external memory (AHB).
All data accesses are to the TCM interface, or to the external memory, depending
on the setting of the base address in the data TCM region register. No protection
checks are made. All addresses are flat mapped. That is, VA = MVA= PA.
All data accesses are to the TCM interface or to external memory, depending on
the setting of the base address in the data TCM region register. All addresses are
flat mapped. That is, VA =MVA = PA.
All data accesses are either from the TCM interface, or from the DCache/AHB
interface, depending on the setting of the base address in the data TCM region
register. Protection checks are made. All addresses are remapped from VA to PA,
depending on the page entry. That is the VA is translated to an MVA, and the
MVA is remapped to a PA.
Table 2-13 Effects of Control Register on TCM interface
ARM DDI0198D