SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 54

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.3.10
2-26
Cache Lockdown and TCM Region Registers c9
31
If either small or large pages are used, and these pages contain subpage access
permissions that are different, then you must use four invalidate TLB single entry
operations, with the MVA set to each subpage, to invalidate all information related to
that page held in a TLB.
Register c9 accesses the Cache Lockdown and TCM Region Registers. The register
accessed is determined by the value of the CRm field:
CRm = c0
CRm = c1
Other values of CRm are reserved.
Cache Lockdown Register c9
The Cache Lockdown Register uses a cache-way-based locking scheme (Format C) that
enables you to control each cache way independently.
These registers enable you to control which cache ways of the four-way cache are used
for the allocation on a linefill. When the registers are defined, subsequent linefills are
only placed in the specified target cache way. This gives you some control over the
cache pollution caused by particular applications, and provides a traditional lockdown
operation for locking critical code into the cache.
A locking bit for each cache way determines if the normal cache allocation is allowed
to access that cache way. See Table 2-21 on page 2-28.
A maximum of three cache ways of the four-way associative cache can be locked,
ensuring that normal cache line replacement is performed.
If no cache ways have L bits set to 0, then cache way 3 is used for all linefills.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Note
Modified virtual address
selects the Cache Lockdown Register
selects the TCM Region Register.
Figure 2-11 Register c8 MVA format
10 9
SBZ
ARM DDI0198D
0