SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 69

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.2
ARM DDI0198D
Address translation
The VA generated by the CPU core is converted to a Modified Virtual Address (MVA)
by the FCSE using the value held in CP15 c13. The MMU translates MVAs into
physical addresses to access external memory, and also performs access permission
checking.
The MMU table-walking hardware is used to add entries to the TLB. The translation
information that comprises both the address translation data and the access permission
data resides in a translation table located in physical memory. The MMU provides the
logic for automatically traversing this translation table and loading entries into the TLB.
The number of stages in the hardware table walking and permission checking process
is one or two depending on whether the address is marked as a section-mapped access
or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access.
Page-mapped accesses are for:
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The translation process always begins in the same way, with a level one fetch. A
section-mapped access requires only a level one fetch, but a page-mapped access
requires an additional level two fetch.
The following subsections are:
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Copyright © 2001-2003 ARM Limited. All rights reserved.
large pages
small pages
tiny pages.
Translation table base on page 3-6
First-level fetch on page 3-8
First-level descriptor on page 3-8
Section descriptor on page 3-10
Coarse page table descriptor on page 3-11
Fine page table descriptor on page 3-12
Translating section references on page 3-13
Second-level descriptor on page 3-14
Translating large page references on page 3-16
Translating small page references on page 3-18
Translating tiny page references on page 3-19.
Memory Management Unit
3-5