SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 73

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
31
Coarse page table base address
Section base address
Fine page table base address
A section descriptor provides the base address of a 1MB block of memory.
The page table descriptors provide the base address of a page table that contains
second-level descriptors. There are two sizes of page table:
•
•
First-level descriptor bit assignments are shown in Table 3-2.
Bits
Section
[31:20]
[19:12]
[11:10]
[9]
[8:5]
[4]
Copyright © 2001-2003 ARM Limited. All rights reserved.
coarse page tables have 256 entries, splitting the 1MB that the table describes into
4KB blocks
fine page tables have 1024 entries, splitting the 1MB that the table describes into
1KB blocks.
Coarse
[31:10]
-
-
[9]
[8:5]
[4]
20 19
Fine
[31:12]
-
-
[11:9]
[8:5]
[4]
Description
These bits form the corresponding bits of the physical
address.
Should Be Zero.
Access permission bits. Access permissions and domains on
page 3-3 and Fault address and fault status registers on
page 3-21 show how to interpret the access permission bits.
Should Be Zero.
Domain control bits.
Must be 1.
12 11 10 9 8
AP
Domain
Domain
Domain
Table 3-2 First-level descriptor bits
Figure 3-4 First-level descriptor
5 4 3 2 1 0
1
1 C B 1 0
1
0 0
0 1
1 1
Memory Management Unit
Fault
Coarse page table
Section
Fine page table
3-9