SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 75

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.2.5
ARM DDI0198D
Coarse page table descriptor
31
Section descriptor bit assignments are described in Table 3-4.
A coarse page table descriptor provides the base address of a page table that contains
second-level descriptors for either large page or small page accesses. Coarse page tables
have 256 entries, splitting the 1MB that the table describes into 4KB blocks. Figure 3-6
shows the format of a coarse page table descriptor.
If a coarse page table descriptor is returned from the first-level fetch, a second-level
fetch is initiated.
Bits
[31:20]
[19:12]
[11:10]
[9]
[8:5]
[4]
[3:2]
[1:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Coarse page table base address
Description
Form the corresponding bits of the physical address for a section
Always written as 0
The AP bits specify the access permissions for this section
Always written as 0
Specify one of the 16 possible domains (held in the domain access control register)
that contain the primary access controls
Should be written as 1, for backwards compatibility
These bits (C and B) indicate if the area of memory mapped by this section is
treated as write-back cachable, write-through cachable, noncached buffered, or
noncached nonbuffered
These bits must be 10 to indicate a section descriptor
Figure 3-6 Coarse page table descriptor
Table 3-4 Section descriptor bits
10 9 8
S
B
Z
Domain
Memory Management Unit
5 4 3 2 1 0
1 SBZ 0
1
3-11