SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 81

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
31
31
31
31
31
31
Page base address
Page base address
Coarse page table base address
Coarse page table base address
Translation base
Translation base
Because the upper four bits of the page index and low-order four bits of the coarse page
table index overlap, each coarse page table entry for a large page must be duplicated 16
times (in consecutive memory locations) in the coarse page table.
If a large page descriptor is included in a fine page table, the high-order six bits of the
page index and low-order six bits of the fine page table index overlap. Each fine page
table entry for a large page must therefore be duplicated 64 times.
Translation table base
Second-level descriptor
First-level descriptor
Physical address
Copyright © 2001-2003 ARM Limited. All rights reserved.
16 15
16 15
14 13
14 13
31
12 11 10 9 8 7 6 5 4 3 2 1 0
AP3 AP2 AP1 AP0 C B 0 1
Figure 3-10 Large page translation from a coarse page table
10 9 8
10 9
Table index
Table index
Page index
L2 table index
Domain
5 4 3 2 1 0
1
Modified virtual address
20 19
2 1 0
2 1 0
0 0
0 1
0 0
0
0
L2
table index
16 15
12 11
Memory Management Unit
Page index
3-17
0