SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 85

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3
3.3.1
ARM DDI0198D
MMU faults and CPU aborts
Fault address and fault status registers
The MMU generates an abort on the following types of faults:
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In addition, an external abort can be raised by the external system. This can happen only
for access types that have the core synchronized to the external system:
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Alignment fault checking is enabled by the A bit in CP15 c1. Alignment fault checking
is not affected by whether or not the MMU is enabled. Translation, domain, and
permission faults are only generated when the MMU is enabled.
The access control mechanisms of the MMU detect the conditions that produce these
faults. If a fault is detected as a result of a memory access, the MMU aborts the access
and signals the fault condition to the CPU core. The MMU retains status and address
information about faults generated by the data accesses in the data fault status register
and fault address register (see Fault address and fault status registers).
The MMU also retains status about faults generated by instruction fetches in the
instruction fault status register.
The address information for an instruction side abort is contained in the core link
register r14_abt.
An access violation for a given memory access inhibits any corresponding external
access to the AHB interface, with an abort returned to the CPU core.
On a Data Abort, the MMU places an encoded four-bit value, the fault status, along with
the four-bit encoded domain number, in the data FSR. Similarly, on a Prefetch Abort, in
the instruction FSR (intended for debug purposes only). In addition, the MVA
associated with the Data Abort is latched into the FAR. If an access violation
simultaneously generates more than one source of abort, they are encoded in the priority
given in Table 3-9. The FAR is not updated by faults caused by instruction prefetches.
Copyright © 2001-2003 ARM Limited. All rights reserved.
alignment faults (data accesses only)
translation faults
domain faults
permission faults.
page walks
noncached reads
nonbuffered writes
noncached read-lock-write sequence (SWP).
Note
Memory Management Unit
3-21