SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 91

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.5.1
3.5.2
3.5.3
ARM DDI0198D
Alignment faults
Translation faults
Domain faults
•
•
•
If alignment fault checking is enabled (the A bit in CP15 c1 is set), the MMU generates
an alignment fault on any data word access if the address is not word-aligned, or on any
halfword access if the address is not halfword-aligned, irrespective of whether the
MMU is enabled or not. An alignment fault is not generated on any instruction fetch or
any byte access.
If an access generates an alignment fault, the access sequence aborts without reference
to other permission checks.
There are two types of translation fault:
Section
Page
There are two types of domain fault:
Section
Page
If the specified access is either no access (00), or reserved (10), then either a section
domain fault or page domain fault occurs.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Translation faults
Domain faults
Permission faults on page 3-28.
Note
A section translation fault is generated if the level one descriptor is
marked as invalid. This happens if bits [1:0] of the descriptor are both 0.
A page translation fault is generated if the level one descriptor is marked
as invalid. This happens if bits [1:0] of the descriptor are both 0.
The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
Memory Management Unit
3-27