SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 121
SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 121 of 248
- Download datasheet (2Mb)
5.3.3
ARM DDI0198D
Multi-cycle access timing
If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals
are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so
that the value of DRWAIT/IRWAIT pertains to the following data cycle, which
corresponds to the request cycle for the first data cycle. If there is no active TCM access
then the value on DRWAIT/IRWAIT is ignored. This allows the wait signals to be
generated speculatively.
Figure 5-6 shows how the speculative generation of IRWAIT can be used to generate a
single wait state for every ITCM access.
In cycle T1, IRWAIT is asserted but no request is made.
In cycle T2, IRWAIT is asserted and a request is made.
In cycle T3, IRWAIT is deasserted indicating that the access to A will complete in the
following cycle.
In cycle T4, IRWAIT is asserted and a request is made. The access to A completes.
In cycle T5, IRWAIT is deasserted indicating that the access to B will complete in the
following cycle.
In cycle T6, IRWAIT is asserted. No request is made. The access to B completes.
The logic required for the above example corresponds to the two-state state machine
shown in Figure 5-7 on page 5-14.
Copyright © 2001-2003 ARM Limited. All rights reserved.
IRADDR
IRWAIT
Figure 5-6 Generating a single wait state for ITCM accesses using IRWAIT
IRCS
IRRD
CLK
T1
T2
A
T3
T4
Tightly-Coupled Memory Interface
B
I(A)
T5
T6
I(B)
5-13
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