SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 38
SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 38 of 248
- Download datasheet (2Mb)
Programmer’s Model
2-10
Assoc
M bit
Len
The size of the cache is determined by the Size field and the M bit. The M bit is 0 for
the DCache and ICache. The Size field is bits [21:18] for the DCache and bits [9:6] for
the ICache. The minimum size of each cache is 4KB, and the maximum size is 128KB.
Table 2-7 shows the cache size encoding.
The associativity of the cache is determined by the Assoc field and the M bit. The M bit
is 0 for the DCache and ICache. The Assoc field is bits [17:15] for the DCache and bits
[5:3] for the ICache. Table 2-8 shows the cache associativity encoding.
Copyright © 2001-2003 ARM Limited. All rights reserved.
The Assoc field determines the cache associativity in conjunction with
the M bit.
The multiplier bit determines the cache size and cache associativity
values in conjunction with the Size and Assoc fields. If the cache is
present, M must be set to 0. If the cache is absent, M must be set to 1. For
the ARM926EJ-S processor, M is always set to 0.
The Len field determines the line length of the cache.
Table 2-8 Cache associativity encoding (M=0)
Table 2-7 Cache size encoding (M=0)
Assoc field
b010
Other values
Size field
b0011
b0100
b0101
b0110
b0111
b1000
Associativity
4-way
Reserved
ARM DDI0198D
Cache size
4KB
8KB
16KB
32KB
64KB
128KB
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