SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 42
SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 42 of 248
- Download datasheet (2Mb)
Programmer’s Model
2-14
Effects of Control Register on caches
The bits of the Control Register that directly affect the ICache and DCache behavior are:
•
•
•
Bit
[13]
[12]
[11:10]
[9]
[8]
[7]
[6:3]
[2]
[1]
[0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
the M bit
the C bit
the I bit
Name
V bit
I bit
-
R bit
S bit
B bit
-
C bit
A bit
M bit
Function
Location of exception vectors:
0 = Normal exception vectors selected, address range =
1 = High exception vectors selected, address range =
Set to the value of VINITHI on reset.
ICache enable/disable:
0 = ICache disabled
1 = ICache enabled.
SBZ.
ROM protection.
This bit modifies the ROM protection system. See Domain access
control on page 3-24.
System protection.
This bit modifies the MMU protection system. See Domain access
control on page 3-24.
Endianness: 0 = Little-endian operation 1 = Big-endian operation. Set to
the value of BIGENDINIT on reset.
Reserved. SBO.
DCache enable/disable:
0 = Cache disabled
1 = Cache enabled.
Alignment fault enable/disable:
0 = Data address alignment fault checking disabled
1 = Data address alignment fault checking enabled.
MMU enable/disable:
0 = disabled
1 = enabled.
Table 2-11 Control bit functions register c1 (continued)
.
ARM DDI0198D
to
to
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