ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 105

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

7701E–AVR–02/11
In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare
match between TCNT1 and OCR1x, and set at bottom. In inverting compare output mode, out-
put is set on compare match and cleared at bottom.
Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice
as high as the phase correct and phase and frequency correct PWM modes that use
dual-slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows the use of physically
smaller external components (coils, capacitors, etc.), and hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8, 9, or 10 bits, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2 bits (ICR1 or OCR1A set to 0x0003), and the
maximum resolution is 16 bits (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated by using the following equation:
:
In fast PWM mode the counter is incremented until the counter value matches either one of
the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1
(WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the
following timer clock cycle. The timing diagram for the fast PWM mode is shown in
on page
The TCNT1 value in the timing diagram is shown as a histogram for illustrating the sin-
gle-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small
horizontal lines on the TCNT1 slopes represent compare matches between OCR1x and
TCNT1. The OC1x interrupt flag will be set when a compare match occurs.
Figure 14-7. Fast PWM Mode, Timing Diagram
The timer/counter overflow flag (TOV1) is set each time the counter reaches top. In addition,
the OC1A or ICF1 flag is set on the same timer clock cycle on which TOV1 is set when either
OCR1A or ICR1 is used for defining the top value. If one of the interrupts are enabled, the
interrupt handler routine can be used for updating the top and compare values.
TCNTn
OCnx
OCnx
Period
105. The figure shows fast PWM mode when OCR1A or ICR1 is used to define top.
1
2
Atmel ATtiny24/44/84 [Preliminary]
3
R
FPWM
4
=
5
log
---------------------------------- -
6
log
TOP
2
7
+
1
8
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Figure 14-7
105