ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 120

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

15. Timer/Counter Prescaler
15.1
15.2
120
Prescaler Reset
External Clock Source
Atmel ATtiny24/44/84 [Preliminary]
Timer/counter 0, and 1 share the same prescaler module, but the timer/counters can have dif-
ferent prescaler settings. The description below applies to all timer/counters. Tn is used as a
general name, where n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., it operates independently of the clock select logic of the
timer/counter, and it is shared by the timer/counter Tn. Because the prescaler is not affected
by the timer/counter's clock select, the state of the prescaler will have implications for situa-
tions where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the Tn pin can be used as timer/counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn-
chronized (sampled) signal is then passed through the edge detector.
120
logic. The registers are clocked at the positive edge of the internal system clock (
latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 15-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from when an edge has been applied to the Tn pin to when the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least
one system clock cycle, otherwise there is a risk that a false timer/counter clock pulse could be
generated.
CLK_I/O
shows a functional equivalent block diagram of the Tn synchronization and edge detector
Tn
/256, or f
clk
I/O
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be
T
0
pulse for each positive (CSn2:0 = 7) or negative
D
Q
Edge Detector
Figure 15-1 on page
CLK_I/O
/8, f
7701E–AVR–02/11
Tn_sync
(To Clock
Select Logic)
clk
CLK_I/O
I/O
Tn
). The
). The
/64,