AD6657A Analog Devices, AD6657A Datasheet
AD6657A
Related parts for AD6657A
AD6657A Summary of contents
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... SNR for a 60 MHz bandwidth in the 33% mode 72.8 dBFS SNR for a 65 MHz bandwidth in the 36% mode. (General Description continued on Page 3) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD6657A DRGND DCO±AB 11 DO±AB PORT A 11 D10± ...
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... AD6657A TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 9 Timing Specifications ................................................................ 10 Absolute Maximum Ratings ..................................................... 11 Thermal Characteristics ............................................................ 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 14 Equivalent Circuits ......................................................................... 18 Theory of Operation ...
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... Standard SPI that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. Rev Page AD6657A ...
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... AD6657A SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL Integral Nonlinearity (INL) MATCHING CHARACTERISTIC Offset Error ...
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... Full 64.6 25°C 64.8 25°C 10.6 25°C 10.6 25°C 10.6 25°C 10.6 25°C 10.5 Rev Page AD6657A Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS ...
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... AD6657A Parameter 1 WORST SECOND OR THIRD HARMONIC MHz MHz MHz 170 MHz 250 MHz IN SPURIOUS-FREE DYNAMIC RANGE (SFDR MHz MHz MHz 170 MHz 250 MHz IN WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH MHz ...
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... Full 40 Full 26 Full 2 Full 1.22 Full 0 Full −92 Full −10 Full 26 Full 2 Full 1.22 Full 0 Full −10 Full 38 Full 26 Full 5 Rev Page AD6657A Max Unit V 3.6 V p-p AVDD + 0.2 V 2.0 V 0.8 V +10 µA +10 µA 12 kΩ AVDD V AVDD V 0.6 V +100 µA +100 µA 20 kΩ ...
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... AD6657A Parameter 1 LOGIC INPUT (MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance 2 LOGIC INPUT (PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current ...
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... D0A D0B D0A D0B Rev Page Typ Max 625 185 200 2.7 1.3 0.13 4.0 4.9 4.0 4.9 +6.1 + 0.5 310 D10A D10B D10A D10B D10A D10B D0A D0B D0A D0B D0A D0B AD6657A Unit MHz MSPS rms Cycles Cycles µs µs Cycles ...
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... AD6657A TIMING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 5. Parameter Description SYNC TIMING REQUIREMENTS See Figure 3 for details t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time ...
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... Package Type 144-Ball CSP_BGA ESD CAUTION Rev Page specified for addition, metal in direct contact with the Airflow 1 2 Velocity θ θ m/s 26.9 8.9 1 m/s 24.2 2.5 m/s 23.0 Airflow Velocity JB 0 m/s 14.4 1 m/s 14.0 2.5 m/s 13.9 AD6657A 3 θ Unit JB 6.6 °C/W °C/W °C/W Unit JT 0.23 °C/W 0.50 °C/W 0.53 °C/W ...
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... AD6657A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND VIN+C B AGND AGND C VIN+D AGND D VIN–D VCMD E AGND AVDD F AGND AGND G DRGND DRGND H DRVDD DRVDD J D0–CD D2–CD K D0+CD D2+CD L D1–CD D3–CD M D1+CD D3+CD Table 9. Pin Function Descriptions Pin No. Mnemonic A5 AVDD D9 E11 ...
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... Data Clock LVDS Output for Channel C and Channel D—Complement. Input Mode Select Pin. Logic low enables NSR; logic high disables NSR. Input Digital Synchronization Pin. Input Power-Down Input (Active High). Input SPI Clock. Input/Output SPI Data. Input SPI Chip Select (Active Low). Rev Page AD6657A ...
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... AD6657A TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32,000 sample, T unless otherwise noted. 0 185MSPS 10.3MHz @ –1dBFS SNR = 65.6dB (66.6dBFS) –20 SFDR = 94.0dBc –40 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 5. Single Tone FFT, f ...
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... FREQUENCY (MHz) Figure 15. Single Tone FFT 230.3 MHz, NSR Enabled IN in 36% BW Mode, Tuning Word = 14 100 90 SFDR (dBFS) 80 SNR (dBFS SFDR (dBc SNR (dBc INPUT AMPLITUDE (dBFS) Figure 16. Single Tone SNR/SFDR vs. Input Amplitude ( 70.3 MHz IN AD6657A ), IN ...
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... AD6657A 100 90 SFDR (dBFS) 80 SNR (dBFS SFDR (dBc SNR (dBc INPUT AMPLITUDE (dBFS) Figure 17. Single Tone SNR/SFDR vs. Input Amplitude ( 140.3 MHz IN 95 SFDR (dBc SNR (dBFS INPUT FREQUENCY (MHz) Figure 18. Single Tone SNR/SFDR vs. Input Frequency (f 1 ...
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... 1500 2000 Rev Page 0.20 0.15 0.10 0. 500 1000 1500 OUTPUT CODE Figure 26. DNL 30.3 MHz DUTY CYCLE (%) Figure 27. SNR vs. Duty Cycle 10.3 MHz IN AD6657A 2000 65 70 ...
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... AD6657A EQUIVALENT CIRCUITS AVDD VIN Figure 28. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 29. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 30. Equivalent LVDS Output Circuit AVDD AVDD SYNC 16kΩ 0.9V Figure 31. Equivalent SYNC Input Circuit AVDD CLK– ...
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... VCMx pins. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCMx pin voltage (typically 0.5 × AVDD). The VCMx pins must be decoupled to ground by a 0.1 µF capacitor. Rev Page AD6657A Note, Frequency Domain Response of AN-827 Application Note, A Resonant BIAS S ...
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... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve ADA4938-2 is easily the true SNR performance of the AD6657A. For applications in (see Figure 36), and the which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 38). In this ...
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... For the popular IF band of 140 MHz, Figure 40 shows an example of a 1:4 transformer passive configuration where a differential inductor is used to resonate with the internal input capacitance of the AD6657A. This configuration realizes excellent noise and distortion performance. Figure 41 shows an example of an active front-end configuration using the able gain amplifier (VGA) ...
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... This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6657A. Noise and distortion performance are nearly flat for 0.1µF 100Ω a wide range of duty cycles with the DCS enabled. ...
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... Figure 49. SNR vs. Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD6657A, treat the clock input as an analog signal. Separate power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... Rev Page Data Sheet AD6657A AD6657A is 40 MSPS. provides a data clock output (DCO) signal Twos Complement Mode 100 0000 0000 100 0000 0000 000 0000 0000 ...
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... Figure 51. 22% BW Mode, Tuning Word = 13 185MSPS 140.3MHz @ –1dBFS NSR 22% BW MODE SNR = 73.4dB (75.0dBFS) SFDR = 91dBc THIRD HARMONIC 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) /4 Tuning) S 185MSPS 140.3MHz @ –1dBFS NSR 22% BW MODE SNR = 73.4dB (75.0dBFS) SFDR = 91dBc THIRD HARMONIC 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 53. 22% BW Mode, Tuning Word = 41 AD6657A ...
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... CENTER 0 ADC 0.33 × ADC Figure 54 to Figure 56 show the typical spectrum that can be expected from the AD6657A in the 33% BW mode for three different tuning words. 0 185MSPS 140.3MHz @ –1dBFS NSR 33% BW MODE –20 SNR = 70.9dB (72.5dBFS) SFDR = 91dBc –40 – ...
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... MODE pin allows for very flexible control of the NSR feature on a per channel basis. /4 Tuning) S Rev Page 185MSPS 140.3MHz @ –1dBFS NSR 36% BW MODE SNR = 70.4dB (72.0dBFS) SFDR = 91dBc THIRD HARMONIC 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 59. 36% BW Mode, Tuning Word = 28 AD6657A ...
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... A built-in self test (BIST) feature is included that verifies the integrity of the digital datapath of the AD6657A. Various output test options are also provided to place predictable values on the outputs of the AD6657A. ...
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... Three pins define the SPI of the AD6657A: SCLK, SDIO, and CSB (see Table 12). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the AD6657A. SDIO (serial data input/output bidirectional pin that allows data to be sent to and read from the internal memory map registers ...
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... Address 0x13), this address location should not be written. Default Values After the AD6657A is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13). Logic Levels An explanation of logic level terminology follows: ...
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... Clock divide phase 000 = 0 input clock cycles delayed 001 = 1 input clock cycle delayed 010 = 2 input clock cycles delayed Open Open Open Open Rev Page AD6657A Default (LSB) Value Bit 1 Bit 0 (Hex) Comments LSB first Open 0x18 Nibbles are ...
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... AD6657A Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x0D Test mode Open Open (local) 0x0E BIST enable Open Open (local) 0x10 Offset adjust Open Open (local) 0x14 Output mode Open Open (local) 0x15 Output Open Open adjust (local) 0x16 Clock phase ...
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... NSR mode NSR 0x00 enable 0 = off (used only if Bit otherwise ignored) 0x1C AD6657A Comments Read only. Read only. Control register to synchronize the clock divider. Noise shaping requantizer (NSR) controls. NSR frequency tuning word. ...
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... AD6657A NSR Tuning Word (Register 0x3E) Bits[7:6]—Reserved Bits[5:0]—NSR Tuning Word The NSR tuning word sets the band edges of the NSR band. In 22% BW mode, there are 57 possible tuning words; in 33% BW mode, there are 34 possible tuning words; in 36% BW mode, there are 28 possible tuning words. For either mode, each step represents 0 ...
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... Locate these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane is sufficient when using the AD6657A. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved ...
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... Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Rev Page BALL CORNER BOTTOM VIEW 0.65 MIN 0.25 MIN 0.50 COPLANARITY 0.45 0.20 0.40 BALL DIAMETER Package Option BC-144-1 BC-144-1 www.analog.com/AD6657A Data Sheet ...