AD9628 Analog Devices, AD9628 Datasheet

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AD9628

Manufacturer Part Number
AD9628
Description
12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9628

Resolution (bits)
12bit
# Chan
2
Sample Rate
125MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip,SE-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9628BCPZ-105
Manufacturer:
AD
Quantity:
10
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 71.2 dBFS @ 70 MHz
SFDR = 93 dBc @ 70 MHz
Low power: 74 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.25 LSB
Serial port control options
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand-held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
1
Rev.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
This product is protected by a U.S patent.
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
GSM, EDGE, W-CDMA, LTE,
0
alignment
CDMA2000, WiMAX, TD-SCDMA
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SENSE
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
RBIAS
VIN+B
VIN+A
VIN–A
VIN–B
VREF
12-Bit, 125/105 MSPS, 1.8 V Dual
VCM
SEE FIGURE 7 FOR LVDS PIN NAMES.
The
supply and features a separate digital output driver supply
to accommodate 1.8 V CMOS or LVDS logic families.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/data timing and
offset adjustments.
The
LFCSP that is pin compatible with the AD9650/AD9269/
AD9268
ADCs, the
10-bit ADCs, enabling a simple migration path between
10-bit and 16-bit converters sampling from 20 MSPS to
125 MSPS.
CLK+ CLK–
SELECT
AD9628
AD9628
REF
Analog-to-Digital Converter
AVDD
FUNCTIONAL BLOCK DIAGRAM
16-bit ADC, the
AD9231
1
is packaged in a 64-lead RoHS-compliant
operates from a single 1.8 V analog power
AGND
DIVIDE
1 TO 8
SYNC
ADC
ADC
©
2011
12-bit ADC, and the
AD9628
PROGRAMMING DATA
Figure 1.
DUTY CYCLE
STABILIZER
Analog Devices, Inc. All rights reserved.
SDIO
AD9258/AD9251/AD9648
DCS
SCLK
SPI
CSB
PDWN DFS
CONTROLS
MODE
AD9608/AD9204
AD9628
www.analog.com
OEB
ORA
D11A
D0A
DCOA
DRVDD
ORB
D11B
D0B
DCOB
14-bit

Related parts for AD9628

AD9628 Summary of contents

Page 1

... ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2011 Analog Devices, Inc. All rights reserved. AD9628 CSB ORA D11A D0A DCOA DRVDD ORB D11B ...

Page 2

... Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 19 AD9628-125 ................................................................................ 19 AD9628-105 ................................................................................ 22 Equivalent Circuits ......................................................................... 24 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Analog Input Considerations .................................................... 25 REVISION HISTORY 7/11—Revision 0: Initial Version   Voltage Reference ....................................................................... 27   ...

Page 3

... V CMOS or LVDS output logic levels are supported. Output data can also be multiplexed onto a single output bus. The AD9628 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent. Rev Page AD9628 ...

Page 4

... Full 2 Full 5 Full 7.5 Full 0.9 Full 0.5 1.3 Full 1.7 1.8 1.9 Full 1.7 1.8 1.9 Full 79.0 84 Full 17.0 Full 56.0 Rev Page AD9628-125 Min Typ Max Unit 12 Bits Guaranteed −1.0 −0.3 +0.4 % FSR 0.2 ±5.0 % FSR ±0.6 LSB ±0.25 LSB ±0.75 LSB ±0.3 LSB ±0.01 ±0.6 % FSR ±1.0 ±4.0 % FSR ±2 ppm/° ...

Page 5

... Full −82 25°C −89 25°C −83 Rev Page AD9628 AD9628-125 Min Typ Max Unit 148 mW 201 212 mW 269 mW 120 mW 2.0 mW AD9628-125 Min Typ Max Unit 71.5 dBFS 71.4 dBFS 71.2 dBFS 70.2 dBFS 70.9 dBFS 69.6 dBFS 71.4 dBFS 71.3 dBFS 71.1 dBFS 70 dBFS 69.8 dBFS 68.3 dBFS 11 ...

Page 6

... MHz 650 AD9628-105/125 Typ Max Unit CMOS/LVDS/LVPECL 0.9 V 3.6 V p-p AVDD + 0.2 V 1.4 V +10 μA +10 μ kΩ DRVDD + 0.2 V 0.6 V +10 μA 132 μA 26 kΩ ...

Page 7

... Full 1.22 Full 0 Full −90 Full −10 Full 26 Full 5 Full 1.79 Full 1.75 Full Full Full 290 345 Full 1.15 1.25 Full 160 200 Full 1.15 1.25 Rev Page AD9628 Max Unit pF DRVDD + 0.2 V 0.6 V +10 µA 128 µA kΩ pF DRVDD + 0.2 V 0.6 V −134 µA +10 µA kΩ 0.2 V 0.05 V 400 mV 1 ...

Page 8

... Full 4.76 Full 1.0 Full 0.07 Full 1.8 2.9 4.4 Full 2.0 3.1 4.4 Full −1.2 −0.1 +1.0 Full 2.4 Full 2.4 Full −0.20 +0.03 +0.25 Full 16 Full 16/16.5 Full 350 Full 250 Full 2 Rev Page AD9628-125 Min Typ Max Unit 1000 MHz 20 125 MSPS 10 125 MSPS 1.0 ns 0.07 ps rms 1.8 2.9 4.4 ns 2.0 3.1 4.4 ns −1.2 −0.1 +1.0 ns 2.4 ns 2.4 ns − ...

Page 9

... N – – Figure 2. CMOS Default Output Mode Data Output Timing Rev Page Limit 0.24 0. – – – 12 AD9628 Unit ns typ ns typ ns min ns min ns min ns min ns min ns min ns min ns min ns min ...

Page 10

... AD9628 N – 1 VIN t CH CLK+ CLK– DCOA/DCOB CH A DATA CH B DATA VIN CLK+ CLK– DCO– DCO+ D0+ (LSB) D0– (LSB) PARALLEL INTERLEAVED MODE D11+ (MSB) D11– (MSB) D1+/D0+ (LSB) CHANNEL D1–/D0– (LSB) MULTIPLEXED MODE D11+/D10+ (MSB) CHANNEL A D11– ...

Page 11

... CLK SSYNC HSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev Page AD9628 ...

Page 12

... AD9628 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical 1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D11A/D11B to AGND DCOA/DCOB to AGND ...

Page 13

... Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Digital Synchronization Pin. Slave mode only. Rev Page AD9628 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS ...

Page 14

... AD9628 Pin No. Mnemonic Type Digital Outputs 30 D0A (LSB) Output 31 D1A Output 32 D2A Output 33 D3A Output 34 D4A Output 35 D5A Output 36 D6A Output 38 D7A Output 39 D8A Output 40 D9A Output 41 D10A Output 42 D11A (MSB) Output 43 ORA Output 8 D0B (LSB) Output 9 D1B Output 11 D2B Output ...

Page 15

... Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Digital Synchronization Pin. Slave mode only. Rev Page AD9628 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS ...

Page 16

... AD9628 Pin No. Mnemonic Type Digital Outputs 14 D0+ (LSB) Output 13 D0− (LSB) Output 16 D1+ Output 15 D1− Output 18 D2+ Output 17 D2− Output 21 D3+ Output 20 D3− Output 23 D4+ Output 22 D4− Output 27 D5+ Output 26 D5− Output 30 D6+ Output 29 D6− ...

Page 17

... Reference Mode Selection. Input/Output External Reference Bias Resistor. Output Common-Mode Level Bias Output for Analog Inputs. Input ADC Clock Input—True. Input ADC Clock Input—Complement. Input Digital Synchronization Pin. Slave mode only. Rev Page AD9628 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 SDIO/DCS 43 ...

Page 18

... AD9628 Pin No. Mnemonic Digital Outputs 11 B D1−/D0−(LSB D1+/D0+(LSB D3−/D2− D3+/D2 D5−/D4− D5+/D4 D7−/D6− D7+/D6 D9−/D8− D9+/D8 D11−/D10− (MSB D11+/D10+ (MSB D1−/D0−(LSB) ...

Page 19

... SNR = 70.1dB (71.1dBFS) –20 SFDR = 91.6dBc –40 –60 – FREQUENCY (MHz) Figure 12. Single-Tone FFT with f = 100.5 MHz IN 0 125MSPS 200.5MHz AT –1dBFS SNR = 68.8dB (69.8dBFS) SFDR = 85.0dBc FREQUENCY (MHz) Figure 13. Single-Tone FFT with f = 200.5 MHz IN AD9628 ...

Page 20

... AD9628 0 –15 –30 –45 –60 –75 2F1 – F2 –90 + –105 –120 –135 FREQUENCY (MHz) Figure 14. Two-Tone FFT with MHz and f IN1 100 SNRFS AT 25° 100 150 ANALOG INPUT FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale ...

Page 21

... N – – OUTPUT CODE Figure 21. Shorted Input Histogram 1.0 0.5 0 –0.5 –1.0 3000 3500 4000 Rev Page 500 1000 1500 2000 2500 3000 3500 OUTPUT CODE Figure 22. INL Error with f = 9.7 MHz IN AD9628 4000 ...

Page 22

... AD9628 AD9628-105 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 105MSPS 9.7MHz AT –1dBFS SNR = 70.8dB (71.8dBFS) SFDR = 94dBc –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 23. Single-Tone FFT with f ...

Page 23

... MHz IN Rev Page SFDR (dBc) SNR (dBFS SAMPLE RATE (MSPS) Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70.1 MHz 500 1000 1500 2000 2500 3000 OUTPUT CODE Figure 33. INL Error with f = 9.7 MHz IN AD9628 85 95 105 3500 4000 ...

Page 24

... AD9628 EQUIVALENT CIRCUITS AVDD VIN±x Figure 34. Equivalent Analog Input Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 35. Equivalent Clock Input Circuit DRVDD PAD Figure 36. Equivalent Digital Output Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ ...

Page 25

... See the AN-742 Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Rev Page AD9628 is a differential switched PAR H C ...

Page 26

... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9628. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 46). ...

Page 27

... Figure 48. Single-Ended Input Configuration VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9628. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference ...

Page 28

... Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz) sample clock CLOCK INPUT CLK– 2pF Rev Page has a very flexible clock input structure. The clock AD9628 (at clock rates GHz prior to internal CLK AD9628 AD9628 ® Mini-Circuits ADT1-1WT, 1:1 Z 0.1µF 0.1µF XFMR 100Ω 50Ω ...

Page 29

... This allows the user to CLK+ provide a wide range of clock input duty cycles without affecting 100Ω ADC the performance of the AD9628. Noise and distortion perform- 0.1µF CLK– ance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 58. ...

Page 30

... Figure 60. AD9628-125 Power and Current vs. Clock Rate (1.8 V CMOS 90 AN-756 Application Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS Rev Page × C × f × N DRVDD ...

Page 31

... AGND DRVDD Digital Output Enable Function (OEB) The AD9628 has a flexible three-state ability for the digital output pins. The three-state mode is enabled through the SPI interface and can subsequently be controlled using the OEB pin or through the SPI. Once enabled via the SPI (Bit 7) in Register 0x101, and the OEB pin is low, the output data drivers and DCOs are enabled ...

Page 32

... A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the is included. Various output test options are also provided to place predictable values on the outputs of the AD9628. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9628 signal path ...

Page 33

... For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t CLK t LOW A11 A10 Figure 62. Serial Port Interface Timing Diagram Rev Page DON’T CARE AD9628 DON’T CARE ...

Page 34

... The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9628. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

Page 35

... If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 18 affect the entire part or the channel features for which independent settings are not allowed between channels. Rev Page AD9628 ...

Page 36

... Global Open Open clock (global) 0x0B Clock Open Open divide (global) Bit 5 Bit 4 Bit 3 Soft reset 1 1 8-bit chip ID[7:0] AD9628 = 0x89 Open Open Open Open Open Open External Open Open power- down pin function 0 = PDWN 1 = standby Open Open Open Open ...

Page 37

... Internal V digital adjustment 0x04 REF 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2 0x00 AD9628 Comments Chop mode enabled if Bit 2 is enabled. When this register is set, the test data is placed on the output pins in place of normal data Configures the outputs ...

Page 38

... AD9628 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x1A User B15 B14 Pattern 1 MSB (global) 0x1B User B7 B6 Pattern 2 LSB (global) 0x1C User B15 B14 pattern MSB 0x24 MISR LSB 0x25 MISR MSB 0x2A Overrange Open Open control (global) 0x2E Output ...

Page 39

... For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct-conversion receivers, chopping in the first stage of the AD9628 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise where it can be filtered ...

Page 40

... AD9628 User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled (default). Bits[6:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus ...

Page 41

... LVDS mode. This additional DRVDD current does not cause damage to the AD9628, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the can be disabled at power-up by taking the PDWN pin high ...

Page 42

... TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9628BCPZ-105 −40°C to +85°C AD9628BCPZ-125 −40°C to +85°C AD9628BCPZRL7-105 −40°C to +85°C AD9628BCPZRL7-125 −40°C to +85°C AD9628-125EBZ RoHS Compliant Part. 0.60 MAX 48 0.50 8.75 BSC BSC SQ 0.50 33 0.40 0.30 0.80 MAX ...

Page 43

... NOTES Rev Page AD9628 ...

Page 44

... AD9628 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09976-0-7/11(0) Rev Page ...

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