AD9628 Analog Devices, AD9628 Datasheet - Page 18

• Manufacturer Part Number: AD9628
• Description: 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9628

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9628
Pin No.
Digital Outputs
11
12
13
14
15
16
17
18
20
21
22
23
29
30
32
31
34
33
36
35
39
38
41
40
43
42
25
24
SPI Control
45
44
46
ADC Configuration
47
48
Mnemonic
B D1−/D0−(LSB)
B D1+/D0+(LSB)
B D3−/D2−
B D3+/D2+
B D5−/D4−
B D5+/D4+
B D7−/D6−
B D7+/D6+
B D9−/D8−
B D9+/D8+
B D11−/D10− (MSB)
B D11+/D10+ (MSB)
A D1−/D0−(LSB)
A D1+/D0+(LSB)
A D3−/D2−
A D3+/D2+
A D5+/D4+
A D5−/D4−
A D7+/D6+
A D7−/D6−
A D9+/D8_
A D9−/D8−
A D11+/D10+(MSB)
A D11−/D10−(MSB)
OR+
OR−
DCO+
DCO−
SCLK/DFS
SDIO/DCS
CSB
OEB
PDWN
Input
Input/Output
Input
Input
Input
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Rev. 0 | Page 18 of 44
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Output Enable Input (Active Low). Pin must be enabled via SPI.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Description
Channel B LVDS Output Data 1/Data 0—Complement.
Channel B LVDS Output Data 1/Data 0—True.
Channel B LVDS Output Data 3/Data 2—Complement.
Channel B LVDS Output Data 3/Data 2—True.
Channel B LVDS Output Data 5/Data 4—Complement.
Channel B LVDS Output Data 5/Data 4—True.
Channel B LVDS Output Data 7/Data 6—Complement.
Channel B LVDS Output Data 7/Data 6—True.
Channel B LVDS Output Data 9/Data 8—Complement.
Channel B LVDS Output Data 9/Data 8—True.
Channel B LVDS Output Data 11/Data 10—Complement.
Channel B LVDS Output Data 11/Data 10—True.
Channel A LVDS Output Data 1/Data 0—Complement.
Channel A LVDS Output Data 1/Data 0—True.
Channel A LVDS Output Data 3/Data 2—Complement.
Channel A LVDS Output Data 3/Data 2—True.
Channel A LVDS Output Data 5/Data 4—Complement.
Channel A LVDS Output Data 5/Data 4—True.
Channel A LVDS Output Data 7/Data 6—Complement.
Channel A LVDS Output Data 7/Data 6—True.
Channel A LVDS Output Data 9/Data 8—Complement.
Channel A LVDS Output Data 9/Data 8—True.
Channel A LVDS Output Data 11/Data 10—Complement.
Channel A LVDS Output Data 11/Data 10—True.
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.