AD9628 Analog Devices, AD9628 Datasheet - Page 3

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AD9628

Manufacturer Part Number
AD9628
Description
12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9628

Resolution (bits)
12bit
# Chan
2
Sample Rate
125MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip,SE-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
GENERAL DESCRIPTION
The
125 MSPS/105 MSPS analog-to-digital converter (ADC). It
features a high performance sample-and-hold circuit and on-
chip voltage reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 12-bit accuracy at
125 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
AD9628
is a monolithic, dual-channel, 1.8 V supply, 12-bit,
Rev. 0 | Page 3 of 44
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, Gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. 1.8 V CMOS or LVDS output logic levels are supported.
Output data can also be multiplexed onto a single output bus.
The
is specified over the industrial temperature range (−40°C to
+85°C). This product is protected by a U.S. patent.
AD9628
is available in a 64-lead RoHS-compliant LFCSP and
AD9628

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