AD9628 Analog Devices, AD9628 Datasheet - Page 6

• Manufacturer Part Number: AD9628
• Description: 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9628

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9628
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST OTHER (HARMONIC OR SPUR)
TWO-TONE SFDR
CROSSTALK
ANALOG INPUT BANDWIDTH
1
2
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK/DFS/SYNC)
See the AN-835 Application Notes, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
f
f
f
f
f
f
f
f
f
f
f
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 9.7 MHz
= 30.5 MHz
= 70 MHz
= 100 MHz
= 200 MHz
= 9.7 MHz
= 30.5 MHz
= 70 MHz
= 100 MHz
= 200 MHz
= 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
1
2
1
2
Temp
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
Min
82
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Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9628-105
Typ
92
90
90
89
83
−96
−95
−95
−93
−92
85
−95
650
Min
0.3
AGND − 0.3
0.9
−10
−10
8
1.22
0
−10
40
1.22
0
−92
−10
Max
−87
CMOS/LVDS/LVPECL
AD9628-105/125
Min
85
Typ
0.9
4
10
26
2
26
2
AD9628-125
Typ
92
90
93
90
84
−94
−94
−95
−92
−91
85
−95
650
Max
3.6
AVDD + 0.2
1.4
+10
+10
12
DRVDD + 0.2
0.6
+10
132
DRVDD + 0.2
0.6
−135
+10
Max
−87
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF