AD9628 Analog Devices, AD9628 Datasheet - Page 8

• Manufacturer Part Number: AD9628
• Description: 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9628

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9628
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
1
2
3
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 2 in SPI Register 0x17 (see Table 18).
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Out-of-Range Recovery Time
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
CMOS Mode (DRVDD = 1.8 V)
LVDS Mode (DRVDD = 1.8 V)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency) Channel A/Channel B
Wake-Up Time (Power Down)
Wake-Up Time (Standby)
Data Propagation Delay (t
DCO Propagation Delay (t
DCS Enabled
DCS Disabled
DCO to Data Skew (t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
1
A
)
SKEW
SKEW
CH
)
)
)
DCO
PD
PD
DCO
3
J
)
)
)
)
)
2
CLK
2
)
Rev. 0 | Page 8 of 44
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
20
10
1.8
2.0
−1.2
−0.20
AD9628-105
Typ
9.52
4.76
1.0
0.07
2.9
3.1
−0.1
2.4
2.4
+0.03
16
16/16.5
350
250
2
Max
1000
105
105
4.4
4.4
+1.0
+0.25
Min
20
10
1.8
2.0
−1.2
−0.20
AD9628-125
Typ
8
4
1.0
0.07
2.9
3.1
−0.1
2.4
2.4
+0.03
16
16/16.5
350
250
2
Max
1000
125
125
4.4
4.4
+1.0
+0.25
Unit
MHz
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
µs
ns
Cycles