AD9648 Analog Devices, AD9648 Datasheet - Page 34

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AD9648

Manufacturer Part Number
AD9648
Description
14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9648

Resolution (bits)
14bit
# Chan
2
Sample Rate
125MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p,2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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AD9648
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of the
AD9648. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 16 describes the strappable functions supported
on the AD9648.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the duty cycle stabilizer, output
data format, and power-down feature control. In this mode, the
CSB chip select bar should be connected to AVDD, which
disables the serial port interface.
AD9648
to prevent these signals from transi-
AN-812
Application Note, Micro-
Rev. 0 | Page 34 of 44
When the device is in SPI mode, the PDWN and OEB Pins (if
enabled) remain active. For SPI control of output enable and
power-down, the OEB and PDWN pins should be set to their
default states.
Table 16. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
SPI ACCESSIBLE FEATURES
Table 17 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the
via SPI. The
following Table 18, the external memory map register table.
Table 17. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
AN-877
AD9648
External Voltage
DRVDD (default)
AGND
DRVDD
AGND (default)
DRVDD
AGND (default)
DRVDD
AGND (default)
Application Note, Interfacing to High Speed ADCs
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
including LVDS
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
part-specific features are described in detail
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby
Normal operation

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