AD6649 Analog Devices, AD6649 Datasheet - Page 19

• Manufacturer Part Number: AD6649
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

Data Sheet
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6649.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference voltage
changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6649 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased
internally (see Figure 31) and require no external bias. If the
inputs are floated, the CLK− pin is pulled low to prevent spurious
clocking.
Clock Input Options
The AD6649 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 32 and Figure 33 show two preferable methods for clocking
the AD6649 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD6649 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD6649
while preserving the fast rise and fall times of the signal, which
are critical to low jitter performance.
CLOCK
INPUT
Figure 32. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLK+
Figure 31. Simplified Equivalent Clock Input Circuit
50Ω
390pF
4pF
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
XFMR
AVDD
0.9V
®
390pF
390pF
SCHOTTKY
HSMS2822
DIODES:
4pF
CLK–
CLK+
CLK–
ADC
Rev. A | Page 19 of 40
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
as shown in Figure 34. The AD9510, AD9511, AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, AD9524, and
drivers offer excellent jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 35. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers
offer excellent jitter performance.
Input Clock Divider
The AD6649 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD6649 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
CLOCK
INPUT
INPUT
INPUT
Figure 33. Balun-Coupled Differential Clock (Up to 625 MHz)
50kΩ
50kΩ
Figure 35. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 34. Differential PECL Sample Clock (Up to 625 MHz)
390pF
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
AD95xx
PECL DRIVER
ADCLK905/ADCLK907/ADCLK925
AD95xx
LVDS DRIVER
25Ω
25Ω
240Ω
390pF
390pF
SCHOTTKY
HSMS2822
DIODES:
240Ω
0.1µF
0.1µF
100Ω
0.1µF
0.1µF
100Ω
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
AD6649
ADC
ADC
clock