AD7608 Analog Devices, AD7608 Datasheet - Page 24

• Manufacturer Part Number: AD7608
• Description: 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7608

• Resolution (bits): 18bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7608
DIGITAL INTERFACE
The AD7608 provides two interface options: a parallel interface
and high speed serial interface. The required interface mode is
selected via the
The operation of the interface modes is discussed in the
following sections.
PARALLEL INTERFACE (PAR/SER SEL = 0)
Data can be read from the AD7608 via the parallel data bus with
standard
bus, the
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both
The rising edge of the
and the falling edge of the
of the high impedance state.
enables the data lines, it is the function that allows multiple
AD7608 devices to share the same parallel data bus.
Figure 42. AD7608 interface diagram—One AD7608 Using the Parallel Bus;
PAR
A A
CS
A A
E E
A A
and
/ SER SEL pin should be tied low. The
E E
A A
PAR
A A
RD
A A
AD7608
RD/SCLK
E E
A A
DB[15:0]
signals. To read the data over the parallel
/ SER SEL pin.
E E
A A
CS
A A
BUSY
E E
A A
CS
A A
and
CS
E E
A A
input signal three-states the bus
A A
A A
RD
CS
14
13
12
[33:24]
[22:16]
CS
A A
CS
A A
E E
A A
Shorted Together
E E
A A
input signal takes the bus out
INTERRUPT
E E
A A
and
E E
A A
is the control signal that
RD
A A
E E
A A
are logic low.
DIGITAL
HOST
CS
A A
E E
A A
and
RD
A A
Rev. A | Page 24 of 32
E E
A A
The
signal can be used to access the conversion results as shown
in Figure 4. A read operation of new data can take place after
the BUSY signal goes low (Figure 2), or alternatively a read
operation of data from the previous conversion process can
take place while BUSY is high (Figure 3).
The
results register. Two
18-bit conversion result from each channel. Applying a sequence
of 16
results out from each channel onto the 16-bit parallel output
bus in ascending order. The first
goes low clocks out DB[17:2] of the V1 result, the next
falling edge updates the bus with DB[1:0] of V1 result. It takes
16
the AD7608. On the AD7608, the 16
out the DB[1:0] conversion result for Channel V8. When the
RD
A A
each channel to be transferred to the digital host (DSP, FPGA).
When there is only one AD7608 in a system/board and it does
not share the parallel bus, data can be read using just one control
signal from the digital host. The
together as shown in Figure 5. In this case, the data bus comes
out of three-state on the falling edge of
CS
A A
and to be read by the digital host. In this case,
frame the data transfer of each data channel. In this case, 16
pulses are required to read the eight channels of data.
E E
A A
RD
A A
E E
A A
and
signal is logic low, it enables the data conversion result from
CS
A A
RD
A A
RD
A A
E E
A A
pulses to read the eight 18-bit conversion results from
E E
A A
RD
A A
signal can be permanently tied low, and the
E E
A A
pin is used to read data from the output conversion
E E
A A
pulses to the AD7608
E E
A A
signal allows the data to be clocked out of the AD7608
A A
RD
E E
A A
pulses are required to read the full
RD
A A
CS
A A
RD
A A
E E
A A
E E
A A
pin clocks the conversion
and
E E
A A
th
falling edge after BUSY
falling edge of
CS
A A
RD
A A
/
E E
A A
RD
A A
E E
A A
signals can be tied
. The combined
E E
A A
Data Sheet
CS
A A
E E
A A
is used to
RD
A A
RD
A A
RD
A A
E E
A A
E E
A A
clocks
E E
A A
CS
A A
E E
A A