AD7608 Analog Devices, AD7608 Datasheet - Page 25

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AD7608

Manufacturer Part Number
AD7608
Description
8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7608

Resolution (bits)
18bit
# Chan
8
Sample Rate
200kSPS
Interface
Par,Ser,SPI
Analog Input Type
Diff-Bip
Ain Range
Bip 10V,Bip 5.0V
Adc Architecture
SAR
Pkg Type
QFP

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Data Sheet
SERIAL INTERFACE (PAR/SER SEL = 1)
To read data back from the AD7608 over the serial interface,
the
signals are used to transfer data from the AD7608. The AD7608
has two serial data output pins, D
read back from the AD7608 using one or both of these D
lines. For the AD7608, conversion results from Channel V1 to
Channel V4 first appear on DOUTA while conversion results from
Channel V5 to Channel V8 first appear on D
The
and D
the conversion result. The rising edge of SCLK clocks all
subsequent data bits onto the serial data outputs, D
and D
serial read, or it can be pulsed to frame each channel read
of 18 SCLK cycles.
Figure 43 shows a read of eight simultaneous conversion results
using two D
transfer is used to access data from the AD7608 and
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using just one D
to access all conversion data as the channel data is output in
ascending order. For the AD7608 to access all eight conversion
results on one D
These 144 SCLK cycles can be framed by one
group of 18 SCLK cycles can be individually framed by the
signal. The disadvantage of using just one D
throughput rate is reduced if reading after conversion. The
unused DOUT line should be left unconnected in serial mode.
For the AD7608, if DOUTB is used as a single DOUT line, the
channel results will output in the following order: V5, V6, V7,
V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns
low once V5 is read on D
Figure 6 shows the timing diagram for reading one channel of
data, framed by the
A A
PAR
CS
A A
OUT
OUT
E E
A A
falling edge takes the data output lines (D
/ SER SEL pin should be tied high. The
E E
A A
B) out of three-state and clocks out the MSB of
B. The
OUT
lines on the AD7608. In this case, a 72 SCLK
CS
A A
OUT
E E
A A
OUT
input can be held low for the entire
line, a total of 144 SCLK cycles are required.
CS
line, in which case D
E E
A A
signal, from the AD7608 in serial mode.
OUT
D
D
B.
SCLK
OUT
OUT
CS
A
B
OUT
A, and D
OUT
OUT
OUT
A is recommended
OUT
CS
A A
Figure 43. AD7608 Serial Interface with two D
CS
A A
line is that the
B.
E E
A A
B. Data can be
signal or each
OUT
E E
A A
V1
V5
and SCLK
OUT
A
CS
A
E E
A A
is held
OUT
CS
A A
Rev. A | Page 25 of 32
E E
A A
V2
V6
The SCLK input signal provides the clock source for the serial
read operation.
The falling edge of
clocks out the MSB of the 18-bit conversion result. This MSB
is valid on the first falling edge of the SCLK after the
edge. The subsequent 17 data bits are clocked out of the AD7608
on the SCLK rising edge. Data is valid on the SCLK falling edge.
Eighteen clock cycles must be provided to the AD7608 to access
each conversion result.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the
output pin is in three-state. In serial mode, the falling edge of
CS
A A
pin high indicating that the result from V1 is available on the
D
logic low following the 18
are read on D
when V1 is output on the serial data output pin. It only goes
high when V1 is available on D
available on D
READING DURING CONVERSION
Data can be read from the AD7608 while BUSY is high and
conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read may be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a V
Data can be read from the AD7608 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t
outlined in Table 3, should be observed in this condition.
V3
V7
OUT
E E
A A
takes FRSTDATA out of three-state and sets the FRSTDATA
A output data line. The FRSTDATA output returns to a
OUT
Lines
OUT
OUT
V4
V8
CS
A A
B, the FRSTDATA output does not go high
B).
E E
A A
goes low to access the data from the AD7608.
CS
A A
72
E E
A A
takes the bus out of three-state and
th
SCLK falling edge. If all channels
DRIVE
OUT
of 3.3 V to 5.25 V.
CS
A A
A (and this is when V5 is
E E
A A
input is high, the FRSTDATA
AD7608
CS
A A
E E
A A
falling
6
, as

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