AD7608 Analog Devices, AD7608 Datasheet - Page 8

• Manufacturer Part Number: AD7608
• Description: 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7608

• Resolution (bits): 18bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7608
Parameter
1
2
3
Timing Diagrams
Sample tested during initial release to ensure compliance. All input signals are specified with t
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
t
t
t
27
28
29
CONVST A/
CONVST A/
CONVST A/
CONVST A/
FRSTDATA
CONVST B
CONVST B
CONVST B
CONVST B
DB[15:0]
RESET
RESET
DATA:
BUSY
BUSY
RD
CS
CS
CS
Min
INVALID
Limit at T
t
t
8
13
t
24
t
26
t
t
7
7
Typ
t
t
t
MIN
RESET
RESET
10
Figure 3. CONVST x Timing—Reading During a Conversion
[17:2]
t
t
5
5
Figure 2.CONVST x Timing—Reading After a Conversion
V1
, T
Figure 4. Parallel Mode Separate
MAX
Max
19
24
17
22
24
t
t
1
1
t
[1:0]
11
V1
Unit
ns
ns
ns
ns
ns
Rev. A | Page 8 of 32
Description
Delay from
V
V
Delay from 16
V
V
Delay from
DRIVE
DRIVE
DRIVE
DRIVE
t
[17:2]
27
V2
t
14
= 3.3 V to 5.25 V
= 2.3 V to 2.7 V
= 3.3 V to 5.25 V
= 2.3 V to 2.7 V
R D
A A
C S
A A
t
t
A A
t
CS
t
CYCLE
CYCLE
CONV
[1:0]
CONV
V2
t
t
th
E E
A A
E E
A A
3
3
E E
A A
R
and
rising edge until FRSTDATA three-state enabled
falling edge to FRSTDATA low
= t
SCLK falling edge to FRSTDATA low
F
A A
RD
= 5 ns (10% to 90% of V
E E
A A
Pulses
t
6
[17:2]
V8
t
15
t
4
DD
[1:0]
V8
) and timed from a voltage level of 1.6 V.
t
t
t
16
17
29
t
9
t
t
2
2
Data Sheet