AD9484 Analog Devices, AD9484 Datasheet - Page 21

• Manufacturer Part Number: AD9484
• Description: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9484

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr.
(Hex)
10
0D
0F
14
15
16
17
Register Name
Offset
TEST_IO
AIN_CONFIG
OUTPUT_MODE
OUTPUT_ADJUST
OUTPUT_PHASE
FLEX_OUTPUT_DELAY
0
0
0
Output
clock
polarity
1 =
inverted
0 =
normal
(default)
Bit 7
(MSB)
0
00 = Pattern 1 only
11 = toggle P1/P2/
01 = toggle P1/P2
(For user-defined
Bits[3:0] = 1000)
mode only, set
10 = toggle
P1/0000
0000
Bit 6
0
0
0
0
0
Bit 5
Reset
PN23
gen:
1 = on
0 = off
(default)
0
0
0
0
0
8-bit device offset adjustment [7:0]
1000 0000 = −128 codes
0111 111 = +127 codes
Rev. A | Page 21 of 24
Bit 4
Reset
PN9
gen:
1 = on
0 = off
(default)
0
Output
enable:
0 =
enable
(default)
1 =
disable
0
0
0
0000 0000 = 0 codes
Bit 3
0
0
LVDS
course
adjust:
0 =
3.5 mA
(default)
1 =
2.0 mA
0
(Format determined by OUTPUT_MODE)
0100 = checker board output
0111 = one/zero word toggle
0101 = PN23 sequence
0001 = midscale short
Bit 2
1000 = user defined
Analog
input
disable:
1 = on
0 = off
(default)
Output
invert:
1 = on
0 = off
(default)
0
Output clock delay:
0000 = off (default)
Output test mode:
0010 = +FS short
0011 = −FS short
0100 = reserved
1010 = unused
1001 = unused
1011 = unused
1100 = unused
0001 = −1/10
0010 = −2/10
0011 = −3/10
0101 = +5/10
0110 = +4/10
0111 = +3/10
1000 = +2/10
1001 = +1/10
0110 = PN9
0000 = 0
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
Bit 1
0
0
Data format select:
00 = offset binary
10 = Gray code
complement
01 = twos
(default)
Bit 0
(LSB)
0
0
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0
Default Notes/
Comments
Device offset
trim: codes are
relative to the
output
resolution.
When set, the
test data is
placed on the
output pins in
place of normal
data.
Set pattern
values:
P1 = Reg 0x19,
Reg 0x1A
P2 = Reg 0x1B,
Reg 0x1C
0
Shown as
fractional value
of sampling
clock period
that is
subtracted or
added to initial
t
Figure 2
SKEW
AD9484
, see
.