AD9643 Analog Devices, AD9643 Datasheet - Page 15

• Manufacturer Part Number: AD9643
• Description: 14-Bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9643

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Pin No.
Digital Outputs
SPI Control
Output Enable Bar and Power-
Down
7
6
8
9
11
12
13
14
15
16
17
18
20
21
22
23
26
27
29
30
31
32
33
34
35
36
38
39
40
41
43
42
25
24
45
44
46
47
48
B D10−/D11−
B D10+/D11+
A D10−/D11−
DCO+
SCLK
CSB
Mnemonic
ORB+
ORB−
B D0−/D1− (LSB)
B D0+/D1+ (LSB)
B D2−/D3−
B D2+/D3+
B D4−/D5−
B D4+/D5+
B D6−/D7−
B D6+/D7+
B D8−/D9−
B D8+/D9+
B D12−/D13− (MSB)
B D12+/D13+ (MSB)
A D0−/D1− (LSB)
A D0+/D1+ (LSB)
A D2−/D3−
A D2+/D3+
A D4−/D5−
A D4+/D5+
A D6−/D7−
A D6+/D7+
A D8−/D9−
A D8+/D9+
A D10+/D11+
A D12−/D13− (MSB)
A D12+/D13+ (MSB)
ORA+
ORA−
DCO−
SDIO
OEB
PDWN
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/Output
Input
Input
Input
Rev. B | Page 15 of 36
Channel B LVDS Output Data 10/Data 11—True.
Description
Channel B LVDS Overrange Output—True. The overrange
indication is valid on the rising edge of the DCO.
Channel B LVDS Overrange Output—Complement. The
overrange indication is valid on the rising edge of the DCO.
Channel B LVDS Output Data 0/Data 1—Complement.
Channel B LVDS Output Data 0/Data 1—True.
Channel B LVDS Output Data 2/Data 3—Complement.
Channel B LVDS Output Data 2/Data 3—True.
Channel B LVDS Output Data 4/Data 5—Complement.
Channel B LVDS Output Data 4/Data 5—True.
Channel B LVDS Output Data 6/Data 7—Complement.
Channel B LVDS Output Data 6/Data 7—True.
Channel B LVDS Output Data 8/Data 9—Complement.
Channel B LVDS Output Data 8/Data 9—True.
Channel B LVDS Output Data 10/Data 11—Complement.
Channel B LVDS Output Data 12/Data 13—Complement.
Channel B LVDS Output Data 12/Data 13—True.
Channel A LVDS Output Data 0/Data 1—Complement.
Channel A LVDS Output Data 0/Data 1—True.
Channel A LVDS Output Data 2/Data 3—Complement.
Channel A LVDS Output Data 2/Data 3—True.
Channel A LVDS Output Data 4/Data 5—Complement.
Channel A LVDS Output Data 4/Data 5—True.
Channel A LVDS Output Data 6/Data 7—Complement.
Channel A LVDS Output Data 6/Data 7—True.
Channel A LVDS Output Data 8/Data 9—Complement.
Channel A LVDS Output Data 8/Data 9—True.
Channel A LVDS Output Data 10/Data 11—Complement.
Channel A LVDS Output Data 10/Data 11—True.
Channel A LVDS Output Data 12/Data 13—Complement.
Channel A LVDS Output Data 12/Data 13—True.
Channel A LVDS Overrange Output—True. The overrange
indication is valid on the rising edge of the DCO.
Channel A LVDS Overrange Output—Complement. The
overrange indication is valid on the rising edge of the DCO.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—
Complement.
SPI Serial Clock.
SPI Serial Data Input/Output.
SPI Chip Select (Active Low).
Output Enable Bar Input (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-
down or standby (see Table 14).
AD9643