AD9284 Analog Devices, AD9284 Datasheet

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AD9284

Manufacturer Part Number
AD9284
Description
8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9284

Resolution (bits)
8bit
# Chan
2
Sample Rate
250MSPS
Interface
Par
Analog Input Type
Diff-Bip,SE-Uni
Adc Architecture
Pipelined
Pkg Type
CSP
FEATURES
Single 1.8 V supply operation
SNR: 49.3 dBFS at 200 MHz input at 250 MSPS
SFDR: 65 dBc at 200 MHz input at 250 MSPS
Low power: 314 mW at 250 MSPS
On-chip reference and track-and-hold
1.2 V p-p analog input range for each channel
Differential input with 500 MHz bandwidth
LVDS-compliant digital output
DNL: ±0.2 LSB
Serial port control options
Pin-programmable power-down function
Available in 48-lead LFCSP
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Battery-powered instruments
Handheld scope meters
Low cost digital oscilloscopes
OTS: video over fiber
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Built-in selectable digital test pattern generation
VIN+A
VIN–A
VIN–B
VIN+B
CLK+
CLK–
VREF
VCM
V
1.0V
REF
SELECT
RBIAS
REF
FUNCTIONAL BLOCK DIAGRAM
×1.5
AGND
ADC
ADC
AVDD
MANAGEMENT
Figure 1.
CLOCK
PWDN
SDIO/
DRVDD
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Analog-to-Digital Converter (ADC)
GENERAL DESCRIPTION
The
converter (ADC) that supports simultaneous operation and is
optimized for low cost, low power, and ease of use. Each ADC
operates at up to a 250 MSPS conversion rate with outstanding
dynamic performance.
The ADC requires a single 1.8 V supply and an encode clock for
full performance operation. No external reference components
are required for many applications. The digital outputs are LVDS
compatible.
The AD9284 is available in a Pb-free, 48-lead LFCSP that is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
CSB
SPI
DRGND
AD9284
SCLK
Integrated Dual 8-Bit, 250 MSPS ADC.
Single 1.8 V Supply Operation with LVDS Outputs.
Power-Down Option Controlled via a Pin-Programmable
Setting.
GENERATION
AD9284
DCO
8-Bit, 250 MSPS, 1.8 V Dual
OE
is a dual 8-bit, monolithic sampling, analog-to-digital
DCO+
DCO–
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL A)
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL B)
©2011 Analog Devices, Inc. All rights reserved.
AD9284
www.analog.com

Related parts for AD9284

AD9284 Summary of contents

Page 1

... The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9284 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. ...

Page 2

... AD9284 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 SPI Timing Specifications ........................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Equivalent Circuits ...

Page 3

... Max Unit Bits ±0.2 ±0.4 LSB ±0.1 ±0.3 LSB Guaranteed ±0.4 ±2 ±2.5 ±2 ±0.5 ±2 ±0.1 ±0 ±2 ppm/°C ±20 ppm/°C 1.2 V p-p 1 kΩ 250 fF 700 MHz 0.98 0. kΩ 1.8 1.9 V 1.8 1.9 V 124 128 314 330 mW 0.3 1.7 mW AD9284 ...

Page 4

... AD9284 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = −1.0 dBFS differential input, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR 10.3 MHz MHz 96.6 MHz 220 MHz IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD 10.3 MHz MHz 96.6 MHz ...

Page 5

... Full 1.2 Full 0 Full 50 57 Full −5 −0.4 25°C 30 25°C 2 Full 290 345 Full 1.15 1.25 Offset binary Rev Page AD9284 Max Unit p-p AVDD + 1.6 V 3.6 V 0.8 V +10 μA +10 μA kΩ pF DRVDD + 0 μA −50 μA kΩ pF DRVDD + 0 ...

Page 6

... AD9284 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate CLK Period (t ) CLK CLK Pulse Width High ( DATA OUTPUT PARAMETERS Data Propagation Delay ( DCO Propagation Delay (t ...

Page 7

... V to AVDD + 0.2 V Table 7. Thermal Resistance −0 DRVDD + 0.3 V Package Type −0 DRVDD + 0.3 V 48-Lead LFCSP (CP-48-12) −0 DRVDD + 0.3 V −65°C to +125°C ESD CAUTION −40°C to +85°C 300°C 150°C Rev Page AD9284 θ θ Unit JA JC 30.4 2.9 °C/W ...

Page 8

... D5+ 21 D5− 20 D4+ 19 D4− AVDD 1 PIN 1 AVDD 2 INDICATOR DNC 3 DNC 4 RBIAS 5 AD9284 DNC 6 TOP VIEW DRGND 7 (Not to Scale) DRVDD D1– 11 D1+ 12 GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 3. Pin Configuration Type Description Supply Analog Power Supply (1 ...

Page 9

... Channel A/Channel B LVDS Data Clock Output—True. Output Channel A/Channel B LVDS Data Clock Output—Complement. Input SPI Serial Clock. Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). Input SPI Chip Select (Active Low). N/A Do Not Connect. Do not connect to this pin. Rev Page AD9284 ...

Page 10

... AD9284 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample 25°C, unless otherwise noted 250MSPS 4.3MHz @ –1dBFS SNR = 48.3dB (49.3dBFS) –20 ENOB = 7.7 SFDR = 70.3dBc –40 SECOND HARMONIC –60 THIRD HARMONIC – ...

Page 11

... OUTPUT CODE Figure 11. DNL Error with f = 4.3 MHz IN 50.0 0.15 0.10 49.8 0.05 49.6 0 49.4 –0.05 49.2 –0.10 49.0 –0.15 225 250 0 = 2.4 MHz 192 224 256 Rev Page AD9284 128 160 192 224 OUTPUT CODE Figure 12. INL Error with f = 4.3 MHz IN 256 ...

Page 12

... AD9284 EQUIVALENT CIRCUITS AVDD AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 13. Clock Inputs AVDD BUF VIN+ 8kΩ BUF AVDD 8kΩ BUF VIN– Figure 14. Analog Inputs (V CML DRVDD DRVDD 30kΩ 350Ω CSB Figure 15. CSB AVDD CLK– AVDD V CML ~1 ...

Page 13

... See the Memory Map Register Descriptions section for more details. RBIAS The AD9284 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor, which is used to set the master current reference of the ADC core, should have a 1% tolerance ...

Page 14

... CLK+ and CLK− pins via a transformer or capacitors. Clock Input Options The AD9284 has a very flexible clock input structure. The clock input can be an LVDS, LVPECL, or sine wave signal. Each configu- ration that is described in this section applies to CLK+ and CLK−. ...

Page 15

... AD9284. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9284 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...

Page 16

... AD9284 SERIAL PORT INTERFACE (SPI) The AD9284 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

Page 17

... The pins described in Table 9 constitute the physical interface between the programming device of the user and the serial port of the AD9284. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

Page 18

... If the entire address location is open omitted from the SPI map (for example, Address 0x13) and should not be written. Default Values After the AD9284 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 12). ...

Page 19

... Soft reset 8-bit chip ID Speed grade ID 000 = 250 MSPS Open Open Open Open Reset Reset Open PN23 gen PN9 gen Open BIST init Rev Page AD9284 Default Bit 0 Value Bit 1 (LSB) (Hex) LSB first 0 0x18 0x0A Open 0x00 ADC B ADC A 0xFF ...

Page 20

... AD9284 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0F ADC input (global/local) 0x10 Offset (local) 0x14 Output Open mode (local) 0x16 Output DCO invert phase (global) 0x18 Voltage Open reference (global) 0x24 MISR LSB (local) 0x25 MISR MSB (local) Bit 5 Bit 4 ...

Page 21

... External Rev Page AD9284 (V) Full Scale (V) 1.013 1.028 1.044 1.060 1.075 1.091 1.106 1.122 1.138 1.153 1.169 1.184 1.200 1.216 1.231 1.247 1.262 1 ...

Page 22

... VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor. RBIAS The AD9284 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor, which sets the master current reference of the ADC core, should have at least a 1% tolerance. ...

Page 23

... Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-48-12) Dimensions shown in millimeters Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page AD9284 0.30 0.23 0.18 PIN 1 INDICATOR 4.70 EXPOSED 4 ...

Page 24

... AD9284 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09085-0-1/11(0) Rev Page ...

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