AD7298 Analog Devices, AD7298 Datasheet - Page 13

• Manufacturer Part Number: AD7298
• Description: 8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: Analog Devices

Specifications of AD7298

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

CIRCUIT INFORMATION
The AD7298 is a high speed, 8-channel, 12-bit ADC with an
internal temperature sensor. The part can be operated from
a 2.8 V to 3.6 V supply and is capable of throughput rates of
1 MSPS per analog input channel.
The AD7298 provides the user with an on-chip, track-and-hold
ADC and a serial interface housed in a 20-lead LFCSP. The
AD7298 has eight single-ended input channels with channel
repeat functionality, which allows the user to select a channel
sequence through which the ADC can cycle with each conse-
cutive CS falling edge. The serial clock input accesses data from
the part, controls the transfer of data written to the ADC, and
provides the clock source for the successive approximation
ADC. The analog input range for the AD7928 is 0 V to V
The AD7298 operates with one cycle latency, which means that
the conversion result is available in the serial transfer following
the cycle in which the conversion is performed.
The AD7298 includes a high accuracy band gap temperature
sensor, which is monitored and digitized by the 12-bit ADC
to give a resolution of 0.25°C. The AD7298 provides flexible
power management options to allow the user to achieve the best
power performance for a given throughput rate. These options
are selected by programming the partial power-down bit, PPD,
in the control register and using the PD / RST pin.
CONVERTER OPERATION
The AD7298 is a 12-bit successive approximation ADC based
around a capacitive DAC. Figure 20 and Figure 21 show simplified
schematics of the ADC. The ADC is comprised of control logic,
SAR, and a capacitive DAC that are used to add and subtract
fixed amounts of charge from the sampling capacitor to bring
the comparator back into a balanced condition. Figure 20 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on the selected
V
When the ADC starts a conversion (see Figure 21), SW2
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge to
bring the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. Figure 23 shows
the ADC’s transfer functions.
IN
channel.
GND1
V
IN
SW1
A
Figure 20. ADC Acquisition Phase
B
SW2
COMPARATOR
CAPACITIVE
CONTROL
LOGIC
DAC
REF
.
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ANALOG INPUT
Figure 22 shows an equivalent circuit of the analog input struc-
ture of the AD7298. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the internally
generated LDO voltage of 2.5 V (D
This causes the diodes to become forward-biased and start
conducting current into the substrate. The maximum current
these diodes can conduct without causing irreversible damage
to the part is 10 mA. Capacitor C1, in Figure 22, is typically
about 8 pF and can primarily be attributed to pin capacitance.
The Resistor R1 is a lumped component made up of the on
resistance of a switch (track-and-hold switch) and also includes
the on resistance of the input multiplexer. The total resistance is
typically about 155 Ω. The capacitor, C2, is the ADC sampling
capacitor and has a capacitance of 34 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pin. In applications
where harmonic distortion and signal-to-noise ratios are
critical, the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function
of the particular application performance criteria.
ADC Transfer Function
The output coding of the AD7298 is straight binary for the
analog input channel conversion results and twos complement,
for the temperature conversion result. The designed code
transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs,
and so forth). The LSB size is V
ideal transfer characteristic for the AD7298 for straight binary
coding is shown in Figure 23.
GND1
V
V
IN
IN
C1
pF
SW1
A
Figure 22. Equivalent Analog Input Circuit
D
Figure 21. ADC Conversion Phase
D1
D2
CAP
B
SW2
(2.5V)
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
REF
COMPARATOR
R1
/4096 for the AD7298. The
CAP
) by more than 300 mV.
C2
pF
CAPACITIVE
CONTROL
LOGIC
DAC
AD7298