AD7298 Analog Devices, AD7298 Datasheet - Page 19

• Manufacturer Part Number: AD7298
• Description: 8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: Analog Devices

Specifications of AD7298

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

POWER-DOWN MODES
The AD7298 has a number of power conservation modes
of operation that are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for different
application requirements. The power-down modes of operation
of the AD7298 are controlled by the power-down (PPD)
bit in the control register and the PD / RST pin on the device.
When power supplies are first applied to the AD7298, care
should be taken to ensure that the part is placed in the required
mode of operation
Normal Mode
Normal mode is intended for the fastest throughput rate
performance because the user does not have to be concerned
about any power-up times because the AD7298 remains fully
powered on at all times. Figure 28 shows the general diagram
of operation of the AD7298 in this mode. The conversion is
initiated on the falling edge of CS and the track-and-hold enters
hold mode. On the 14
returns to track mode and starts acquiring the analog input, as
described in the
the AD7298 on the DIN line during the first 16 clock cycles of
the data transfer are loaded into the control register (provided
the WRITE bit is 1). The part remains fully powered up in
normal mode at the end of the conversion as long as the PPD
bit is set to 0 in the write transfer during that conversion.
To ensure continued operation in normal mode, the PPD bit
should be loaded with 0 on every data write operation. Sixteen
serial clock cycles are required to complete the conversion and
access the conversion result. For specified performance, the
throughput rate should not exceed 1 MSPS. Once a conversion
is complete and the CS has returned high, a minimum of the
quiet time, t
to initiate another conversion and access the previous conver-
sion result.
QUIET
, must elapse before bringing CS low again
Serial Interface
DOUT
SCLK
DIN
CS
th
PART IS IN
PARTIAL
POWER DOWN
SCLK falling edge, the track-and-hold
CONTROL REGISTER CONFIGURED
1
TO POWER UP DEVICE.
WRITE TO CONTROL
REGISTER, PPD = 0.
section. The data presented to
PART BEGINS TO
POWER UP ON CS
RISING EDGE.
12
16
Figure 29. Partial Power-Down Mode of Operation
t
QUIET
PROGRAMMED IN THIS WRITE OPERATION.
FOR CONVERSION. THE NEXT CYCLE
WILL CONVERT THE FIRST CHANNEL
SELECT ANALOG INPUT CHANNELS
1
REGISTER, SELECT CH1, PPD = 0
Rev. B | Page 19 of 24
WRITE TO THE CONTROL
THE PART IS FULLY
POWERED UP ONCE THE
WRITE TO THE CONTROL
REGISTER IS COMPLETED.
INVALID DATA
Partial Power-Down Mode
In this mode, part of the internal circuitry on the AD7298 is
powered down. The AD7298 enters partial power-down on
the CS rising edge once the current serial write operation
containing 16 SCLK clock cycles is completed. To enter partial
power-down, the PPD bit in the control register should be set
to 1 on the last required read transfer from the AD7298.
Once in partial power-down mode, the AD7298 transmits
all 1s on the DOUT pin if CS is toggled low. If the averaging
feature for the temperature sensor is enabled in the control
register, the averaging is reset once the device enters partial
power-down mode.
The AD7298 remains in partial power-down until the power-
down bit, PPD, in the control register is changed to a logic level
zero (0). The AD7298 begins powering up on the rising edge
of CS following the write to the control register disabling the
power-down bit. Once t
to the control register must be completed to update its content
with the desired channel configuration for the subsequent
conversion. A valid conversion is then initiated on the next CS
falling edge.
Because the AD7298 has one cycle latency, the first conversion
result after exiting partial power-down mode is available in the
fourth serial transfer, as shown in Figure 29. The first cycle
updates the PPD bit, the second cycle updates the configuration
and Channel ID bits, the third completes the conversion, and
the fourth accesses the DOUT valid result. The use of this
mode enables a reduction in the overall power consumption of
the device.
16
t
QUIET
DOUT
SCLK
DIN
CS
RESULT AVAILABLE FOR READING.
Figure 28. Normal Mode Operation
1
AD7298 CONVERTING CHANNEL 1
NEXT CYCLE HAS CHANNEL 1
CONTROL REGISTER
1
DATA WRITTEN TO CONTROL
QUIET
INVALID DATA
NO WRITE TO
4 CHANNEL ADDRESS BITS
+ CONVERSION RESULT
REGISTER IF REQUIRED
has elapsed, a full 16-SCLK write
16
1
6
AD7298