AD7298 Analog Devices, AD7298 Datasheet - Page 21

• Manufacturer Part Number: AD7298
• Description: 8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: Analog Devices

Specifications of AD7298

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for the serial
interface to the AD7298. The serial clock provides the conver-
sion clock and controls the transfer of information to and from
the AD7298 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track on the 14
Figure 30
rising edge of
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated, the DOUT line goes back into tri-
state, and the control register is not updated; otherwise, DOUT
returns to three-state on the 16
clock cycles are required to perform the conversion process and
to access data from the AD7298.
For the AD7298, four-channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to precede the 12 bits of data (see Table 9).
DOUT
SCLK
DIN
CS
at Point B. On the 16
THREE-
STATE
CS , the DOUT line goes back into three-state.
ADD3
t
2
WRITE
t
3
1
ADD2
REPEAT
th
t
th
9
th
SCLK falling edge as shown in
SCLK falling edge or on the
SCLK falling edge. Sixteen serial
2
ADD1
CH0
3
ADD0
t
CH1
10
Figure 30. Serial Interface Timing Diagram
4
DB11
t
CH2
4
Rev. B | Page 21 of 24
5
DB10
CH3
t
6
The CS going low provides the first address bit to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and
12 data bits are clocked out by subsequent SCLK falling edges.
The final bit in the data transfer is valid for reading on the
16
falling edge.
In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge depending on the SCLK
frequency. The first rising edge of SCLK after the CS falling
edge would have the first address bit provided, and the 15
rising SCLK edge would have last data bit provided.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. The 16-bit word read
from the AD7298 always contains four channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result.
th
falling edge having been clocked out on the previous (15
13
EXT_REF
DB2
t
7
B
14
T
SENSE
DB1
AVG
15
t
5
t
ACQUISITION
DB0
PPD
16
t
8
t
QUIET
THREE-
STATE
AD7298
th
th
)