AD7298-1 Analog Devices, AD7298-1 Datasheet - Page 15

• Manufacturer Part Number: AD7298-1
• Description: 8-Channel, 1 MSPS, 10-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7298-1

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

CONTROL REGISTER
The control register of the AD7298-1 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7298-1 on
the falling edge of SCLK. The data is transferred on the DIN
line at the same time that the conversion result is read from the
part. The data transferred on the DIN line corresponds to the
AD7298-1 configuration for the next conversion. This requires
Table 6. Control Register Bit Functions
D15
WRITE
Table 7. Control Register Bit Function Description
Bit
D15
D14
D13 to
D6
D5
D4, D3,
D1
D2
D0
Table 8. Channel Address Bits
ADD3
0
0
0
0
0
0
0
0
MSB
D14
REPEAT
Mnemonic
WRITE
REPEAT
CH0 to
CH7
0
DONTC
EXT_REF
PPD
ADD2
0
0
0
0
1
1
1
1
D13
CH0
Description
The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this
bit is a 1, the following 15 bits are written to the control register. If this bit is a 0, then the remaining 15 bits are not
loaded to the control register, and it remains unchanged.
This bit enables the repeated conversion of the selected sequence of channels.
These eight channel selection bits are loaded at the end of the current conversion and select which analog input
channel is to be converted in the next serial transfer, or they can select the sequence of channels for conversion in
the subsequent serial transfers. Each CHx bit corresponds to an analog input channel. A channel or sequence of
channels is selected for conversion by writing a 1 to the appropriate CHx bit/bits. Channel address bits
corresponding to the conversion result are output on DOUT prior to the 10 bits of data. The next channel to be
converted is selected by the mux on the 14
Zero should be written to this bit.
Don’t care.
Writing Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external
reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected.
This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of
the internal analog circuitry is powered down. The AD7298-1 retains the information in the control register while
in partial power-down mode. The part remains in this mode until a 0 is written to this bit.
D12
CH1
D11
CH2
ADD1
0
0
1
1
0
0
1
1
D10
CH3
D9
CH4
D8
CH5
Rev. A | Page 15 of 24
ADD0
0
1
0
1
0
1
0
1
D7
CH6
th
SCLK falling edge.
D6
CH7
16 serial clocks for every data transfer. Only the information
provided on the first 16 falling clock edges (after the falling
edge of CS ) is loaded to the control register. MSB denotes the
first bit in the data stream. The bit functions are outlined in
Table 6 and Table 7. At power-up, the default content of the
control register is all zeros.
D5
0
Analog Input Channel
V
V
V
V
V
V
V
V
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
D4
DONTC
D3
DONTC
D2
EXT_REF
D1
DONTC
AD7298-1
D0
PPD
LSB